Application specific integrated circuit for physiological monitoring

Claim 2

An application specific integrated circuit for monitoring multi-lead physiological signals from a patient, the integrated circuit comprising: a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being adapted for coupling to the patient for receiving input signals from the patient; a plurality of analog output signal terminals coupled to at least some of said plurality of analog input signal terminals and allowing said input signals to be coupled to an external circuit; a plurality of analog expansion input signal terminals for inputting analog signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said plurality of analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both; and a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals, whereby a set of digital control data bits on said digital control signals selects a combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for processing.

Claim 3

The integrated circuit of claim 1 wherein said plurality of analog output signal terminals are coupled to at least some of said plurality of analog input signal terminals through a buffer circuit having a plurality of inputs and outputs, at least some of said plurality of analog input signal terminals coupled to said buffer circuit inputs, and at least some of said plurality of analog output signal terminals being coupled to said buffer circuit outputs.

Claim 4

The integrated circuit of claim 1, further comprising a plurality of analog filters for receiving said summed output signals and for filtering said summed output signals to provide a set of filtered signals.

Claim 5

The integrated circuit of claim 3 wherein said plurality of analog filters have a plurality of cutoff frequency settings that are individually programmable for each of said plurality of analog filters.

Claim 6

The integrated circuit of claim 3, further comprising a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals.

Claim 7

The integrated circuit of claim 5 wherein said plurality of analog amplifiers have a plurality of gain settings that are individually programmable for each of said plurality of amplifiers.

Claim 8

The integrated circuit of claim 5, further comprising an analog multiplexor with a plurality of analog inputs receiving said set of amplified signals and for selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level.

Claim 9

An ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being adapted for coupling to a plurality of patient electrodes for receiving ECG input signals from said patient electrodes; a plurality of analog output signal terminals coupled to at least some of said plurality of analog input signal terminals and allowing said ECG input signals to be coupled to an external circuit; a plurality of analog expansion input signal terminals for inputting analog signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said plurality of analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both; and a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals, whereby a set of digital control data bits on said digital control signals selects any combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for processing.

Claim 10

An ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being adapted for coupling to a plurality of patient electrodes for receiving ECG input signals from said patient electrodes; a plurality of analog output signal terminals coupled to at least some of said plurality of analog input signal terminals and allowing said ECG input signals to be coupled to an external circuit; a plurality of analog expansion input signal terminals for inputting analog signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said plurality of analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both; and a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals, whereby a set of digital control data bits on said digital control signals selects any combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for processing.

Claim 11

The integrated circuit of claim 8 wherein said plurality of analog output signal terminals are coupled to at least some of said plurality of analog input signal terminals through a buffer circuit having a plurality of inputs and outputs, at least some of said plurality of analog input signal terminals coupled to said buffer circuit inputs, and at least some of said plurality of analog output signal terminals being coupled to said buffer circuit outputs.

Claim 12

The integrated circuit of claim 8, further comprising a plurality of analog filters for receiving said summed output signals and for filtering said summed output signals to provide a set of filtered signals.

Claim 13

The integrated circuit of claim 10 wherein said plurality of analog filters have a plurality of cutoff frequency settings that are individually programmable for each of said plurality of analog filters.

Claim 14

The integrated circuit of claim 10, further comprising a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals.

Claim 15

The integrated circuit of claim 12 wherein said plurality of analog amplifiers have a plurality of gain settings that are individually programmable for each of said plurality of amplifiers.

Claim 16

The integrated circuit of claim 13, further comprising an analog multiplexor with a plurality of analog inputs receiving said set of amplified signals and for selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level.

Claim 17

An ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being adapted for coupling to a plurality of patient electrodes for receiving ECG input signals from said patient electrodes; a buffer circuit having a plurality of buffer inputs and buffer outputs, said plurality of buffer inputs coupled to at least some of said plurality of analog input signal terminals, said plurality of buffer outputs providing buffered versions of said ECG input signals; a plurality of analog output signal terminals coupled to at least some of said plurality of buffer outputs and allowing said ECG input signals to be coupled to an external circuit; a plurality of analog expansion input signal terminals for inputting analog signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said plurality of analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input singals and for outputting a set of summed output signals; a pacer detection circuit responsive to said summed output signals for detecting heart pacemaker pulses and for generating a pacer signal indicating the presence of said pacemaker pulses; a blanking circuit, responsive to said pacer signal, for blanking said set of summed output signals; a plurality of analog filters for receiving said summed output signals and for filtering said summed output signals to provide a set of filtered signals; a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals; an analog multiplexor with a plurality of analog inputs receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level, whereby a set of digital control data bits on said digital control signals select any combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for amplification and processing.

Claim 18

An ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being adapted for coupling to a plurality of patient electrodes for receiving ECG input signals from said patient electrodes; a buffer circuit having a plurality of buffer inputs and buffer outputs, said plurality of buffer inputs coupled to at least some of said plurality of analog input signal terminals, said plurality of buffer outputs providing buffered versions of said ECG input signals; a plurality of analog output signal terminals coupled to at least some of said plurality of buffer outputs and allowing said ECG input signals to be coupled to an external circuit; a plurality of analog expansion input signal terminals for inputting analog signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said plurality of analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input singals and for outputting a set of summed output signals; a pacer detection circuit responsive to said summed output signals for detecting heart pacemaker pulses and for generating a pacer signal indicating the presence of said pacemaker pulses; a blanking circuit, responsive to said pacer signal, for blanking said set of summed output signals; a plurality of analog filters for receiving said summed output signals and for filtering said summed output signals to provide a set of filtered signals; a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals; an analog multiplexor with a plurality of analog inputs receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level, whereby a set of digital control data bits on said digital control signals select any combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for amplification and processing.

Claim 19

An ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: seven analog input signal terminals, at least some of said input signal terminals being adapted for coupling to patient electrodes for receiving ECG input signals from said patient electrodes; a buffer circuit having a seven buffer inputs and seven buffer outputs, said buffer inputs coupled to said analog input signal terminals, said buffer outputs providing buffered versions of said ECG input signals; seven analog output signal terminals coupled to said buffer outputs and allowing said ECG input signals to be coupled to an external circuit; seven analog expansion input signal terminals for inputting analog expansion signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals; a plurality of analog filters for receiving said summed output signals and for filtering said summed output signals to provide a set of filtered signals; a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals; an analog multiplexor with a plurality of analog inputs receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level, whereby a set of digital control data bits on said digital control signals select any combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for amplification and processing.

Claim 20

An ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: seven analog input signal terminals, at least some of said input signal terminals being adapted for coupling to patient electrodes for receiving ECG input signals from said patient electrodes; a buffer circuit having a seven buffer inputs and seven buffer outputs, said buffer inputs coupled to said analog input signal terminals, said buffer outputs providing buffered versions of said ECG input signals; seven analog output signal terminals coupled to said buffer outputs and allowing said ECG input signals to be coupled to an external circuit; seven analog expansion input signal terminals for inputting analog expansion signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals; a plurality of analog filters for receiving said summed output signals and for filtering said summed output signals to provide a set of filtered signals; a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals; an analog multiplexor with a plurality of analog inputs receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level, whereby a set of digital control data bits on said digital control signals select any combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for amplification and processing.

Claim 21

A first and second application specific integrated circuits comprising: a first set of analog input signal terminals within the first integrated circuit, at least some of said first set of input signal terminals receiving a first set of input signals from external analog sources; a buffer circuit within the first integrated circuit receiving said first set of input signal terminals and providing a first set of buffered outputs for each of said first set of input signals; a first set of analog output signal terminals within the first integrated circuit coupled to said buffered outputs allowing said first set of input signals to be coupled to an external circuit; a first set of analog expansion input signal terminals within the first integrated circuit for inputting a first set of analog expansion signals from external analog sources; a first set of digital control input signal terminals responsive to a first set of digital control signals within the first integrated circuit for selecting a number of analog signals from either said first set of analog input signal terminals, said first set of analog expansion input signal terminals, or a combination of both; a first lead summing network within the first integrated circuit, responsive to said first set of digital control signals, for adding said selected number of analog input signals and for outputting a first set of summed output signals; a second set of analog input signal terminals within the second integrated circuit, which may or may not be receiving a second set of input signals from external analog sources; a buffer circuit within the second integrated circuit receiving said second set of input signal terminals and providing buffered outputs for each of said second set of input signals; a second set of analog output signal terminals within the second integrated circuit coupled to said set of buffered output allowing said second set of input signals to be coupled to an external circuit; a second set of analog expansion input signal terminals within the second integrated circuit for inputting a second set of analog expansion signals from external analog sources, including said first set of analog output signal terminals; a second set of digital control input signal terminals responsive to a second set of digital control signals within the second integrated circuit for selecting a number of analog signals from either said second set of analog input signal terminals, said second set of analog expansion input signal terminals, or a combination of both; and a second lead summing network within the second integrated circuit, responsive to said second set of digital control signals, for adding said selected number of analog input signals and for outputting a second set of summed output signals, whereby the first and second integrated circuits produce a combination of analog signals from said first and second sets of analog input signal terminals and said first and second sets of analog expansion input signal terminals in response to a first and second set of digital control data bits on said first and second sets of digital control signals.

Claim 22

A first and second application specific integrated circuits comprising: a first set of analog input signal terminals within the first integrated circuit, at least some of said first set of input signal terminals receiving a first set of input signals from external analog sources; a buffer circuit within the first integrated circuit receiving said first set of input signal terminals and providing a first set of buffered outputs for each of said first set of input signals; a first set of analog output signal terminals within the first integrated circuit coupled to said buffered outputs allowing said first set of input signals to be coupled to an external circuit; a first set of analog expansion input signal terminals within the first integrated circuit for inputting a first set of analog expansion signals from external analog sources; a first set of digital control input signal terminals responsive to a first set of digital control signals within the first integrated circuit for selecting a number of analog signals from either said first set of analog input signal terminals, said first set of analog expansion input signal terminals, or a combination of both; a first lead summing network within the first integrated circuit, responsive to said first set of digital control signals, for adding said selected number of analog input signals and for outputting a first set of summed output signals; a second set of analog input signal terminals within the second integrated circuit, which may or may not be receiving a second set of input signals from external analog sources; a buffer circuit within the second integrated circuit receiving said second set of input signal terminals and providing buffered outputs for each of said second set of input signals; a second set of analog output signal terminals within the second integrated circuit coupled to said set of buffered output allowing said second set of input signals to be coupled to an external circuit; a second set of analog expansion input signal terminals within the second integrated circuit for inputting a second set of analog expansion signals from external analog sources, including said first set of analog output signal terminals; a second set of digital control input signal terminals responsive to a second set of digital control signals within the second integrated circuit for selecting a number of analog signals from either said second set of analog input signal terminals, said second set of analog expansion input signal terminals, or a combination of both; and a second lead summing network within the second integrated circuit, responsive to said second set of digital control signals, for adding said selected number of analog input signals and for outputting a second set of summed output signals, whereby the first and second integrated circuits produce a combination of analog signals from said first and second sets of analog input signal terminals and said first and second sets of analog expansion input signal terminals in response to a first and second set of digital control data bits on said first and second sets of digital control signals.

Claim 23

A first and second application specific integrated circuits for monitoring multi-lead physiological signals from a patient, comprising: a first set of analog input signal terminals within the first integrated circuit, at least some of said first set of input signal terminals being coupled to the patient and receiving a first set of input signals from the patient; a first set of analog output signal terminals within the first integrated circuit coupled to at least some of said first set of analog input signal terminals and allowing said first set of input signals to be coupled to an external circuit; a first set of analog expansion input signal terminals within the first integrated circuit for inputting a first set of analog expansion signals from external analog sources; a first set of digital control input signal terminals responsive to a first set of digital control signals within the first integrated circuit for selecting a number of analog signals from either said first set of analog input signal terminals, said first set of analog expansion input signal terminals, or a combination of both; a first lead summing network within the first integrated circuit, responsive to said first set of digital control signals, for adding said selected number of analog input signals and for outputting a first set of summed output signals; a second set of analog input signal terminals within the second integrated circuit, some of which may or may not be coupled to the patient and receiving a second set of input signals from the patient a second set of analog output signal terminals within the second integrated circuit coupled to at least some of said second set of analog input signal terminals and allowing said second set of input signals to be coupled to an external circuit; a second set of analog expansion input signal terminal within the second integrated circuit for inputting a second set of analog expansion signals from external analog sources, including said first set of analog output signal terminals; a second set of digital control input signal terminals responsive to a second set of digital controls signals within the second integrated circuit for selecting a number of analog signals from either said second set of analog input signal terminals, said second set of analog expansion input signal terminals, or a combination of both; and a second lead summing network within the second integrated circuit, responsive to said second set of digital control signals, for adding said selected number of analog input signals and for outputting a second set of summed output signals, whereby the first and second integrated circuits produce a combination of analog signals from said first and second sets of analog input signal terminals and said first and second sets of analog expansion input signal terminals in response to a first and second set of digital control data bits on said first and second sets of digital control signals.

Claim 24

A first and second application specific integrated circuits for monitoring multi-lead physiological signals from a patient, comprising: a first set of analog input signal terminals within the first integrated circuit, at least some of said first set of input signal terminals being coupled to the patient and receiving a first set of input signals from the patient; a first set of analog output signal terminals within the first integrated circuit coupled to at least some of said first set of analog input signal terminals and allowing said first set of input signals to be coupled to an external circuit; a first set of analog expansion input signal terminals within the first integrated circuit for inputting a first set of analog expansion signals from external analog sources; a first set of digital control input signal terminals responsive to a first set of digital control signals within the first integrated circuit for selecting a number of analog signals from either said first set of analog input signal terminals, said first set of analog expansion input signal terminals, or a combination of both; a first lead summing network within the first integrated circuit, responsive to said first set of digital control signals, for adding said selected number of analog input signals and for outputting a first set of summed output signals; a second set of analog input signal terminals within the second integrated circuit, some of which may or may not be coupled to the patient and receiving a second set of input signals from the patient a second set of analog output signal terminals within the second integrated circuit coupled to at least some of said second set of analog input signal terminals and allowing said second set of input signals to be coupled to an external circuit; a second set of analog expansion input signal terminal within the second integrated circuit for inputting a second set of analog expansion signals from external analog sources, including said first set of analog output signal terminals; a second set of digital control input signal terminals responsive to a second set of digital controls signals within the second integrated circuit for selecting a number of analog signals from either said second set of analog input signal terminals, said second set of analog expansion input signal terminals, or a combination of both; and a second lead summing network within the second integrated circuit, responsive to said second set of digital control signals, for adding said selected number of analog input signals and for outputting a second set of summed output signals, whereby the first and second integrated circuits produce a combination of analog signals from said first and second sets of analog input signal terminals and said first and second sets of analog expansion input signal terminals in response to a first and second set of digital control data bits on said first and second sets of digital control signals.

Claim 25

The integrated circuit of claim 18 wherein said first set of analog output signal terminals are coupled to at least some of said first set of analog input signal terminals through a first buffer circuit having a plurality of inputs and outputs, at least some of said first set of analog input signal terminals coupled to said first buffer circuit inputs, and at least some of said first set of analog output signal terminals being coupled to said first buffer circuit outputs.

Claim 26

The integrated circuit of claim 18 wherein said second set of analog output signal terminals are coupled to at least some of said second set of analog input signal terminals through a second buffer circuit having a plurality of inputs and outputs, at least some of said second set of analog input signal terminals coupled to said second buffer circuit inputs, and at least some of said second set of analog output signal terminals being coupled to said second buffer circuit outputs.

Claim 27

The integrated circuit of claim 18, further including a plurality of analog filters within the first integrated circuit for receiving said first set of summed output signals and for filtering said first set of summed output signals and outputting a first set of filtered signals.

Claim 28

The integrated circuit of claim 21 wherein said plurality of analog filters have a plurality of cutoff frequency settings that are individually programmable for each of said plurality of analog filters.

Claim 29

The integrated circuit of claim 21, further including a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals.

Claim 30

The integrated circuit of claim 23 wherein said plurality of analog amplifiers have a plurality of gain settings that are individually programmable for each of said plurality of amplifiers.

Claim 31

The integrated circuit of claim 23, further comprising an analog multiplexor with a plurality of analog inputs for receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level.

Claim 32

The integrated circuit of claim 18, further including a plurality of analog filters within the second integrated circuit receiving said second set of summed output signals and for filtering said second set of summed output signals and outputting a second set of filtered signals.

Claim 33

The integrated circuit of claim 26 wherein said plurality of analog filters have a plurality of cutoff frequency settings that are individually programmable for each of said plurality of analog filters.

Claim 34

The integrated circuit of claim 26, further compromising a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals.

Claim 35

The integrated circuit of claim 28 wherein said plurality of analog amplifiers have a plurality of gain settings that are individually programmable for each of said plurality of amplifiers.

Claim 36

The integrated circuit of claim 28, further including an analog multiplexor with a plurality of analog inputs for receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level.

Claim 37

A first and second ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, comprising: a first set of analog input signal terminals within the first integrated circuit, at least some of said first set of input signal terminals being adapted for coupling to a plurality of patient electrodes for receiving a first set of ECG input signals from said plurality of patient electrodes; a first set of analog output signal terminals within the first integrated circuit coupled to at least some of said first set of analog input signal terminals and allowing said first set of input signals to be coupled to an external circuit; a first set of analog expansion input signal terminals within the first integrated circuit for inputting a first set of analog expansion signals from external analog sources; a first set of digital control input signal terminals responsive to a first set of digital control signals within the first integrated circuit for selecting a number of analog signals from either said first set of analog input signal terminals, said first set of analog expansion input signal terminals, or a combination of both; a first lead summing network within the first integrated circuit, responsive to said first set of digital control signals, for adding said selected number of analog input signals and for outputting a first set of summed output signals; a second set of analog input signal terminals within the second integrated circuit, which may or may not be coupled to said plurality of patient electrodes and receiving a second set of ECG input signals from said plurality of patient electrodes; a second set of analog output signal terminals within the second integrated circuit coupled to at least some of said second set of analog input signal terminals and allowing said second set of input signals to be coupled to an external circuit; a plurality of analog expansion input signal terminals within the second integrated circuit for inputting analog expansion signals from external analog sources, including said first set of analog output signal terminals; a second set of digital control input signal terminals responsive to a second set of digital control signals within the second integrated circuit for selecting a number of analog signals from either said second set of analog input signal terminals, said second set of analog expansion input signal terminals, or a combination of both; and a second lead summing network within the second integrated circuit, responsive to said second set of digital control signals, for adding said selected number of analog input signals and for outputting a second set of summed output signals, whereby the first and second integrated circuits produce a combination of analog signals from said first and second sets of analog input signal terminals and said first and second sets of analog expansion input signal terminals in response to a first and second set of digital control data bits on said first and second sets of digital control signals.

Claim 38

A first and second ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, comprising: a first set of analog input signal terminals within the first integrated circuit, at least some of said first set of input signal terminals being adapted for coupling to a plurality of patient electrodes for receiving a first set of ECG input signals from said plurality of patient electrodes; a first set of analog output signal terminals within the first integrated circuit coupled to at least some of said first set of analog input signal terminals and allowing said first set of input signals to be coupled to an external circuit; a first set of analog expansion input signal terminals within the first integrated circuit for inputting a first set of analog expansion signals from external analog sources; a first set of digital control input signal terminals responsive to a first set of digital control signals within the first integrated circuit for selecting a number of analog signals from either said first set of analog input signal terminals, said first set of analog expansion input signal terminals, or a combination of both; a first lead summing network within the first integrated circuit, responsive to said first set of digital control signals, for adding said selected number of analog input signals and for outputting a first set of summed output signals; a second set of analog input signal terminals within the second integrated circuit, which may or may not be coupled to said plurality of patient electrodes and receiving a second set of ECG input signals from said plurality of patient electrodes; a second set of analog output signal terminals within the second integrated circuit coupled to at least some of said second set of analog input signal terminals and allowing said second set of input signals to be coupled to an external circuit; a plurality of analog expansion input signal terminals within the second integrated circuit for inputting analog expansion signals from external analog sources, including said first set of analog output signal terminals; a second set of digital control input signal terminals responsive to a second set of digital control signals within the second integrated circuit for selecting a number of analog signals from either said second set of analog input signal terminals, said second set of analog expansion input signal terminals, or a combination of both; and a second lead summing network within the second integrated circuit, responsive to said second set of digital control signals, for adding said selected number of analog input signals and for outputting a second set of summed output signals, whereby the first and second integrated circuits produce a combination of analog signals from said first and second sets of analog input signal terminals and said first and second sets of analog expansion input signal terminals in response to a first and second set of digital control data bits on said first and second sets of digital control signals.

Claim 39

The integrated circuit of claim 31 wherein said first set of analog output signal terminals are coupled to at least some of said first set of analog input signal terminals through a first buffer circuit having a plurality of inputs and outputs, at least some of said first set of analog input signal terminals coupled to said first buffer circuit inputs, and at least some of said first set of analog output signal terminals being coupled to said first buffer circuit outputs.

Claim 40

The integrated circuit of claim 31 wherein said second set of analog output signal terminals are coupled to at least some of said second set of analog input signal terminals through a second buffer circuit having a plurality of inputs and outputs, at least some of said second set of analog input signal terminals coupled to said second buffer circuit inputs, and at least some of said second set of analog output signal terminals being coupled to said second buffer circuit outputs.

Claim 41

The integrated circuit of claim 31, further including a plurality of analog filters within the first integrated circuit for receiving said first set of summed output signals and for filtering said first set of summed output signals and outputting a first set of filtered signals.

Claim 42

The integrated circuit of claim 34 wherein said plurality of analog filters have a plurality of cutoff frequency settings that are individually programmable for each of said plurality of analog filters.

Claim 43

The integrated circuit of claim 34, further including a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals.

Claim 44

The integrated circuit of claim 36 wherein said plurality of analog amplifiers have a plurality of gain settings that are individually programmable for each of said plurality of amplifiers.

Claim 45

The integrated circuit of claim 36, further comprising an analog multiplexor with a plurality of analog inputs for receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level.

Claim 46

The integrated circuit of claim 31, further including a plurality of analog filters within the second integrated circuit for receiving said second set of summed output signals and for filtering said second set of summed output signals and outputting a second set of filtered signals.

Claim 47

The integrated circuit of claim 39 wherein said plurality of analog filters have a plurality of cutoff frequency settings that are individually programmable for each of said plurality of analog filters.

Claim 48

The integrated circuit of claim 39, further comprising a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals.

Claim 49

The integrated circuit of claim 41 wherein said plurality of analog amplifiers have a plurality of gain settings that are individually programmable for each of said plurality of amplifiers.

Claim 50

The integrated circuit of claim 41, further including an analog multiplexor with a plurality of analog inputs for receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level.

Claim 51

A multi-lead ECG amplifier integrated circuit with improved radio frequency interference immunity for monitoring multi-lead ECG signals from a patient, the circuit comprising: an integrated circuit substrate with a reduced ground plane area for reducing capacitive coupling to a chassis and AC line neutral; a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being adapted for coupling to a plurality of patient electrodes for receiving ECG input signals from said patient electrodes; a buffer circuit having a plurality of buffer inputs and buffer outputs, said plurality of buffer inputs coupled to at least some of said plurality of analog input signal terminals, said plurality of buffer outputs providing buffered versions of said ECG input signals; a plurality of analog output signal terminals coupled to at least some of said plurality of buffer outputs and allowing said ECG input signals to be coupled to an external circuit; a plurality of analog expansion input signal terminals for inputting expansion analog signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said plurality of analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals; a plurality of analog filters for receiving said summed output signals and for filtering summed output signals for outputting a set of filtered signals; a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals; an analog multiplexor with a plurality of analog inputs receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level, whereby a set of digital control data bits on said digital control signals selects a combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for processing.

Claim 52

A multi-lead ECG amplifier integrated circuit with improved radio frequency interference immunity for monitoring multi-lead ECG signals from a patient, the circuit comprising: an integrated circuit substrate with a reduced ground plane area for reducing capacitive coupling to a chassis and AC line neutral; a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being adapted for coupling to a plurality of patient electrodes for receiving ECG input signals from said patient electrodes; a buffer circuit having a plurality of buffer inputs and buffer outputs, said plurality of buffer inputs coupled to at least some of said plurality of analog input signal terminals, said plurality of buffer outputs providing buffered versions of said ECG input signals; a plurality of analog output signal terminals coupled to at least some of said plurality of buffer outputs and allowing said ECG input signals to be coupled to an external circuit; a plurality of analog expansion input signal terminals for inputting expansion analog signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said plurality of analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals; a plurality of analog filters for receiving said summed output signals and for filtering summed output signals for outputting a set of filtered signals; a plurality of analog amplifiers for receiving and amplifying said set of filtered signals and for outputting a set of amplified signals; an analog multiplexor with a plurality of analog inputs receiving said set of amplified signals and selecting and coupling one of said amplified signals as a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level, whereby a set of digital control data bits on said digital control signals selects a combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for processing.

Claim 53

An ECG application specific integrated circuit with pacer pulse detection circuitry for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being coupled to a plurality of patient electrodes and receiving ECG input signals from said patient electrodes; a lead summing network responsive to a digital control input signal for adding a selected number of said ECG input signals and providing a set of summed output signals; and a multiplexor selecting a first one of said set of summed output signals containing a pacemaker signal.

Claim 54

An ECG application specific integrated circuit with pacer pulse detection circuitry for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being coupled to a plurality of patient electrodes and receiving ECG input signals from said patient electrodes; a lead summing network responsive to a digital control input signal for adding a selected number of said ECG input signals and providing a set of summed output signals; and a multiplexor selecting a first one of said set of summed output signals containing a pacemaker signal.

Claim 55

The circuit of claim 45, further including a blanking circuit blanking the ECG signals for a first predetermined time or a second predetermined time, said first predetermined time corresponding to said first type of pacer pulse, said second predetermined time corresponding to said second type of pacer pulse.

Claim 56

The circuit of claim 45 wherein said filter is a bandpass filter to remove unwanted ECG signals and respiration monitor signals.

Claim 57

The circuit of claim 45, further including means for automatically switching said multiplexor to select a second one of said summed output signals if one of said plurality of patient electrodes used by said lead summing network to provide said first one of said set of summed output signals becomes disconnected from the patient.

Claim 58

A pacer pulse detection circuit for monitoring ECG signals from a patient and detecting heart pacemaker pulses, the circuit comprising: a filter for passing pacemaker signals and for producing filtered pacer signals; a differentiator for receiving said filtered pacer signals and for producing a positive spike and a negative spike; a plurality of comparators for comparing said positive spike with a predetermined positive threshold and said negative spike with a predetermined negative threshold; and a timer for measuring elapsed time between said spikes and for determining whether said pacer signal is a first type of pacer pulse or a second type of pacer pulse, whereby the ECG signal can be blanked for a period of time corresponding to the duration of said first type of pacer pulse or said second type of pacer pulse.

Claim 59

A pacer pulse detection circuit for monitoring ECG signals from a patient and detecting heart pacemaker pulses, the circuit comprising: a filter for passing pacemaker signals and for producing filtered pacer signals; a differentiator for receiving said filtered pacer signals and for producing a positive spike and a negative spike; a plurality of comparators for comparing said positive spike with a predetermined positive threshold and said negative spike with a predetermined negative threshold; and a timer for measuring elapsed time between said spikes and for determining whether said pacer signal is a first type of pacer pulse or a second type of pacer pulse, whereby the ECG signal can be blanked for a period of time corresponding to the duration of said first type of pacer pulse or said second type of pacer pulse.

Claim 60

The circuit of claim 49, further comprising a blanking circuit for blanking the ECG signals for a first predetermined time or a second predetermined time, said first predetermined time corresponding to said first type of pacer pulse, said second predetermined time corresponding to said second type of pacer pulse.

Claim 61

The circuit of claim 49 wherein said filter is a bandpass filter to remove unwanted ECG signals and respiration monitor signals.

Claim 62

The circuit of claim 50, further comprising means for selecting a first ECG lead from the ECG signals to monitor for pacer pulses from a plurality of ECG leads provided to the pacer pulse detection circuit.

Claim 63

The circuit of claim 51, further comprising means for automatically switching from said first ECG lead to a second of said plurality of ECG leads if said first ECG lead becomes disconnected from the patient.

Claim 64

An ECG application specific integrated circuit with pacer pulse detection circuitry for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being coupled to a plurality of patient electrodes and receiving ECG input signals from said patient electrodes; a plurality of analog expansion input signal terminals for inputting analog signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said plurality of analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; and a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals; a multiplexor for selecting and multiplexing a first one of said set of summed output signals containing a pacemaker signal; a filter for passing said pacemaker signal and for producing a filtered pacer signal; a differentiator for receiving said filtered pacer signal and for producing a positive spike and a negative spike; a plurality of comparators for comparing said positive spike with a predetermined positive threshold and said negative spike with a predetermined negative threshold; and a timer for measuring elapsed time between said spikes and for determining whether said pacer signal is a first type of pacer pulse or a second type of pacer pulse; and a blanking circuit for blanking said set of summed output signals for a first predetermined time or a second predetermined time, said first predetermined time corresponding to said first type of pacer pulse, said second predetermined time corresponding to said second type of pacer pulse.

Claim 65

An ECG application specific integrated circuit with pacer pulse detection circuitry for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: a plurality of analog input signal terminals, at least some of said plurality of input signal terminals being coupled to a plurality of patient electrodes and receiving ECG input signals from said patient electrodes; a plurality of analog expansion input signal terminals for inputting analog signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said plurality of analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; and a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals; a multiplexor for selecting and multiplexing a first one of said set of summed output signals containing a pacemaker signal; a filter for passing said pacemaker signal and for producing a filtered pacer signal; a differentiator for receiving said filtered pacer signal and for producing a positive spike and a negative spike; a plurality of comparators for comparing said positive spike with a predetermined positive threshold and said negative spike with a predetermined negative threshold; and a timer for measuring elapsed time between said spikes and for determining whether said pacer signal is a first type of pacer pulse or a second type of pacer pulse; and a blanking circuit for blanking said set of summed output signals for a first predetermined time or a second predetermined time, said first predetermined time corresponding to said first type of pacer pulse, said second predetermined time corresponding to said second type of pacer pulse.

Claim 66

The circuit of claim 54, further comprising means for automatically switching said multiplexor from first ECG lead to a second of said plurality of ECG leads if said first ECG lead becomes disconnected from the patient.

Claim 67

An ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: seven analog input signal terminals, at least some of said input signal terminals being adapted for coupling to patient electrodes for receiving ECG input signals from said patient electrodes; a buffer circuit having a seven buffer inputs and seven buffer outputs, said buffer inputs coupled to said analog input signal terminals, said buffer outputs providing buffered versions of said ECG input signals; seven analog output signal terminals coupled to said buffer outputs and allowing said ECG input signals to be coupled to an external circuit; seven analog expansion input signal terminals for inputting analog expansion signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals; a pacer detection multiplexor for selecting and multiplexing a first one of said set of summer output signals containing a pacemaker signal; a pacer filter for passing said pacemaker signal and for producing filtered pacer signals; a differentiator for receiving said filtered pacer signals and for producing a positive spike and a negative spike; a plurality of comparators for comparing said positive spike with a predetermined positive threshold and said negative spike with a predetermined negative threshold; a timer for measuring elapsed time between said spikes and for determining whether said pacer signal is a first type of pacer pulse or a second type of pacer pulse; a controller for receiving said elapsed time and for generating a pacer blanking signal for a period of time corresponding to the duration of said first type of pacer pulse or said second type of pacer pulse; a blanking circuit, responsive to said pacer blanking signal, for blanking said set of summed output signals; a plurality of analog filters coupled to said blanking circuit for receiving said summed output signals when said set of summed output signals are not blanked by said blanking circuit and for filtering said summed output signals to provide a set of filtered signals; a plurality of analog amplifiers for receiving said set of filtered signals and for providing a set of amplified signals; an analog multiplexor with a plurality of analog inputs for receiving said set of amplified signals and for selecting and multiplexing one of said amplified signals to a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level, whereby a set of digital control data bits on said digital control signals select any combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for amplification and processing.

Claim 68

An ECG application specific integrated circuit for monitoring multi-lead ECG signals from a patient, the integrated circuit comprising: seven analog input signal terminals, at least some of said input signal terminals being adapted for coupling to patient electrodes for receiving ECG input signals from said patient electrodes; a buffer circuit having a seven buffer inputs and seven buffer outputs, said buffer inputs coupled to said analog input signal terminals, said buffer outputs providing buffered versions of said ECG input signals; seven analog output signal terminals coupled to said buffer outputs and allowing said ECG input signals to be coupled to an external circuit; seven analog expansion input signal terminals for inputting analog expansion signals from external analog sources; a plurality of digital control input signal terminals responsive to a plurality of digital control signals for selecting a number of said analog signals from either said analog input signal terminals, said analog expansion input signal terminals, or a combination of both, for amplification and processing; a lead summing network, responsive to said plurality of digital control signals, for adding said selected number of analog input signals and for outputting a set of summed output signals; a pacer detection multiplexor for selecting and multiplexing a first one of said set of summer output signals containing a pacemaker signal; a pacer filter for passing said pacemaker signal and for producing filtered pacer signals; a differentiator for receiving said filtered pacer signals and for producing a positive spike and a negative spike; a plurality of comparators for comparing said positive spike with a predetermined positive threshold and said negative spike with a predetermined negative threshold; a timer for measuring elapsed time between said spikes and for determining whether said pacer signal is a first type of pacer pulse or a second type of pacer pulse; a controller for receiving said elapsed time and for generating a pacer blanking signal for a period of time corresponding to the duration of said first type of pacer pulse or said second type of pacer pulse; a blanking circuit, responsive to said pacer blanking signal, for blanking said set of summed output signals; a plurality of analog filters coupled to said blanking circuit for receiving said summed output signals when said set of summed output signals are not blanked by said blanking circuit and for filtering said summed output signals to provide a set of filtered signals; a plurality of analog amplifiers for receiving said set of filtered signals and for providing a set of amplified signals; an analog multiplexor with a plurality of analog inputs for receiving said set of amplified signals and for selecting and multiplexing one of said amplified signals to a multiplexor output; and a sample and hold circuit coupled to said multiplexor output to receive said selected one of said amplified signals and, under control of a hold control input, holding the signal level of said selected one of said amplified signals at a substantially constant level, whereby a set of digital control data bits on said digital control signals select any combination of analog signals from said analog input signal terminals and analog expansion input signal terminals for amplification and processing.

Claim 69

The circuit of claim 56 wherein said pacer filter is a bandpass filter to remove unwanted ECG signals and respiration monitor signals.

Claim 70

The circuit of claim 56, further comprising means for automatically switching said pacer detection multiplexor to select a second one of said set of summed output signals if one of said plurality of patient electrodes used by said lead summing network to provide said first one of said set of summed output signals becomes disconnected from the patient.