Graphics data processing apparatus having non-linear saturating operations on multibit color data

Claim 2

A graphics computer system comprising: a. a host processing system including at least one processor, read only memory, random access memory and assorted peripheral devices for forming a complete computer system, said host processing system furnishing host data determining the content of a visual image to be presented; b. graphics memory circuits capable of storing bit mapped display data signals representing said visual image and being capable of storing said host data, said graphics memory circuits being capable of storing instruction signals used for processing said host data and said display data, said host data including a first array of pixels and said display data including a second array of pixels; c. video display circuits connected to said graphics memory circuits, said video display circuits being capable of forming said visual image in response to receipt of said display data from said graphics memory circuits; and d. graphics processors circuit including: i. central processing unit circuits for executing said instructions accessed from said graphics memory circuits, said central processing unit circuits processing at least said host data to produce said display data in response to executing said instructions; and ii. saturation circuits connected to said central processing unit circuits for performing a nonlinear saturating combination on corresponding pixels from said first and second arrays of pixels to produce a third array of pixels from said first and second arrays that have no more than a certain maximum value and no less than a certain minimum value.

Claim 3

A graphics computer system comprising: a. graphics memory circuits capable of storing bit mapped display data signals representing said visual image and being capable of storing source data, said graphics memory circuits being capable of storing instruction signals used for processing said source data and said display data, said source data including a first array of pixels and said display data including a second array of pixels; b. video display circuits connected to said graphics memory circuits, said video display circuits being capable of forming said visual image in response to receipt of said display data from said graphics memory circuits; and c. graphics processors circuit including: i. central processing unit circuits for executing said instructions accessed from said graphics memory circuits, said central processing unit circuits processing at least said source data to produce said display data in response to executing said instructions; and ii. saturation circuits connected to said central processing unit circuits for performing a nonlinear saturating combination on corresponding pixels from said first and second arrays of pixels to produce a third array of pixels from said first and second arrays that have no more than a certain maximum value and no less than a certain minimum value.

Claim 4

A graphics computer system comprising: a. graphics memory circuits capable of storing bit mapped display data signals representing said visual image and being capable of storing source data, said graphics memory circuits being capable of storing instruction signals used for processing said source data and said display data, said source data including a first array of pixels and said display data including a second array of pixels; b. video display circuits connected to said graphics memory circuits, said video display circuits being capable of forming said visual image in response to receipt of said display data from said graphics memory circuits; and c. graphics processors circuit including: i. central processing unit circuits for executing said instructions accessed from said graphics memory circuits, said central processing unit circuits processing at least said source data to produce said display data in response to executing said instructions; and ii. saturation circuits connected to said central processing unit circuits for performing a nonlinear saturating combination on corresponding pixels from said first and second arrays of pixels to produce a third array of pixels from said first and second arrays that have no more than a certain maximum value and no less than a certain minimum value.

Claim 5

A graphics system arrangement comprising: a. host processing system terminals adapted for connection to a host processing system that determines the content of a visual display to be presented to a user by supplying host data; b. graphics memory circuits capable of storing bit mapped display data signals representing said visual image and being capable of storing said host data, said graphics memory circuits being capable of storing instruction signals used for processing said host data and said display data, said host data including a first array of pixels and said display data including a second array of pixels; c. graphics processor circuits connected to said host processing system terminals and said graphics memory circuits, said graphics processor circuits operating to transfer host data received at said host terminals to said graphics memory circuits and to process said host data and display data in response to said instruction signals stored in said graphics memory circuits, said graphics processor circuits including saturation circuits for performing a nonlinear saturating combination on corresponding pixels from said first and second arrays of pixels to produce a third array of pixels from said first and second arrays that have no more than a certain maximum value and no less than a certain minimum value; d. video palette circuits coupled to said graphics memory circuits and operating to convert said bit mapped display data signals from said graphics memory circuits to video level output signals; e. video connector terminals adapted for connection to a video display that presents a visual image to a user in response to received video image signals; and f. converter circuits connected to said video palette signals and said video connector terminals for converting said video level output signals to video image signals at said video connector terminals.

Claim 6

A graphics system arrangement comprising: a. host processing system terminals adapted for connection to a host processing system that determines the content of a visual display to be presented to a user by supplying host data; b. graphics memory circuits capable of storing bit mapped display data signals representing said visual image and being capable of storing said host data, said graphics memory circuits being capable of storing instruction signals used for processing said host data and said display data, said host data including a first array of pixels and said display data including a second array of pixels; c. graphics processor circuits connected to said host processing system terminals and said graphics memory circuits, said graphics processor circuits operating to transfer host data received at said host terminals to said graphics memory circuits and to process said host data and display data in response to said instruction signals stored in said graphics memory circuits, said graphics processor circuits including saturation circuits for performing a nonlinear saturating combination on corresponding pixels from said first and second arrays of pixels to produce a third array of pixels from said first and second arrays that have no more than a certain maximum value and no less than a certain minimum value; d. video palette circuits coupled to said graphics memory circuits and operating to convert said bit mapped display data signals from said graphics memory circuits to video level output signals; e. video connector terminals adapted for connection to a video display that presents a visual image to a user in response to received video image signals; and f. converter circuits connected to said video palette signals and said video connector terminals for converting said video level output signals to video image signals at said video connector terminals.

Claim 7

A display system comprising: a. a display generating a visual image for presentation to a user in response to receiving display data signals; b. memory circuits capable of storing host data, including a first array of pixels, and said display data, including a second array of pixels, and capable of storing instruction signals used for processing said host data and said display data, said memory circuits producing said display data signals from said display data; c. processor circuits including: i. central processing unit circuits for executing said instructions accessed from said graphics memory circuits, said central processing unit circuits processing at least said host data to produce said display data in response to executing said instructions; and ii. special hardware circuits operating in conjunction with said central processing unit circuits to effect particular manipulations of said host data and said display data, said special hardware circuits including saturation circuits connected to said central processing unit circuits for performing a nonlinear saturating combination on corresponding pixels from said first and second arrays of pixels to produce a third array of pixels from said first and second arrays that have no more than a certain maximum value and no less than a certain minimum value; and d. a host system determining the content of said visual image by causing said host data to be placed in said memory circuits.

Claim 8

A display system comprising: a. a display generating a visual image for presentation to a user in response to receiving display data signals; b. memory circuits capable of storing host data, including a first array of pixels, and said display data, including a second array of pixels, and capable of storing instruction signals used for processing said host data and said display data, said memory circuits producing said display data signals from said display data; c. processor circuits including: i. central processing unit circuits for executing said instructions accessed from said graphics memory circuits, said central processing unit circuits processing at least said host data to produce said display data in response to executing said instructions; and ii. special hardware circuits operating in conjunction with said central processing unit circuits to effect particular manipulations of said host data and said display data, said special hardware circuits including saturation circuits connected to said central processing unit circuits for performing a nonlinear saturating combination on corresponding pixels from said first and second arrays of pixels to produce a third array of pixels from said first and second arrays that have no more than a certain maximum value and no less than a certain minimum value; and d. a host system determining the content of said visual image by causing said host data to be placed in said memory circuits.

Claim 9

The display system of claim 4 in which said memory circuits include video RAM with dual ports for display refresh and display update to occur without interference.

Claim 10

A graphics processor comprising: a. host interface circuits adapted to control communication with a host processing system furnishing host data; b. memory interface circuits adapted to control communication of data and instructions with a memory capable of storing display data and said instructions and said host data, said host data including a first array of pixels and said display data including a second array of pixels; c. central processing unit circuits connected to said host interface circuits and said memory interface circuits, said central processing unit circuits for executing said stored instructions, said central processing unit circuits processing at least said host data to produce said display data in response to executing said instructions; and d. special graphics hardware circuits connected to said central processing unit circuits and operating in conjunction with and under control of said central processing unit circuits to process at least said host data in producing said display data, said special graphics hardware circuits including saturation circuits connected to said central processing unit circuits for performing a nonlinear saturating combination on corresponding pixels from said first and second arrays of pixels to produce a third array of pixels from said first and second arrays that have no more than a certain maximum value and no less than a certain minimum value.

Claim 11

A graphics processor comprising: a. host interface circuits adapted to control communication with a host processing system furnishing host data; b. memory interface circuits adapted to control communication of data and instructions with a memory capable of storing display data and said instructions and said host data, said host data including a first array of pixels and said display data including a second array of pixels; c. central processing unit circuits connected to said host interface circuits and said memory interface circuits, said central processing unit circuits for executing said stored instructions, said central processing unit circuits processing at least said host data to produce said display data in response to executing said instructions; and d. special graphics hardware circuits connected to said central processing unit circuits and operating in conjunction with and under control of said central processing unit circuits to process at least said host data in producing said display data, said special graphics hardware circuits including saturation circuits connected to said central processing unit circuits for performing a nonlinear saturating combination on corresponding pixels from said first and second arrays of pixels to produce a third array of pixels from said first and second arrays that have no more than a certain maximum value and no less than a certain minimum value.

Claim 12

A graphic display system comprising: A. processing unit circuits processing bit mapped display data to control the content of a user viewable display, said processing unit circuits including saturation circuits for performing a nonlinear saturating combination on corresponding pixels from first and second arrays of pixels to produce a third array of pixels that have no more than a certain maximum value and no less than a certain minimum value; and B. memory circuits connected to said processing unit circuits and storing bit mapped display data, including said first, second and third arrays of pixels processed by said processing unit circuits, said memory circuits including a multibit serial output adapted to be connected to said user viewable display.

Claim 13

A graphic display system comprising: A. processing unit circuits processing bit mapped display data to control the content of a user viewable display, said processing unit circuits including saturation circuits for performing a nonlinear saturating combination on corresponding pixels from first and second arrays of pixels to produce a third array of pixels that have no more than a certain maximum value and no less than a certain minimum value; and B. memory circuits connected to said processing unit circuits and storing bit mapped display data, including said first, second and third arrays of pixels processed by said processing unit circuits, said memory circuits including a multibit serial output adapted to be connected to said user viewable display.

Claim 14

The graphics display system of claim 7 in which said processing unit circuits execute accessed instructions for processing said bit mapped display data.

Claim 15

The graphics system of claim 8 in which said memory circuits are capable of storing signals representing said instructions.

Claim 16

The structures of claims 1, 2, 3, 4, 6 or 7 in which said nonlinear saturating combination is addition.

Claim 17

The structures of claims 1, 2, 3, 4, 6 or 7 in which said maximum value is a binary color code of all "1"s.

Claim 18

The structures of claims 1, 2, 3, 4, 6, 8 or 7 in which said nonlinear saturating combination is subtraction.

Claim 19

The structures of claims 1, 2, 3, 4, 6, 8 or 7 in which said minimum value is a binary color code of all "0"s.

Claim 20

The structures of claims 1, 2, 3, 4, 6, 8 or 7 in which said saturation circuits perform said nonlinear saturating combination on plural pixels in parallel.

Claim 21

The structures of claims 1, 2, 3, 4, 6, 8 or 7 in which said saturation circuits include groups of gates for each bit of data.

Claim 22

The structures of anyone of claims 1, 2, or 3 in which said graphics memory circuits include video RAM with dual ports for display refresh and display update to occur without interference.

Claim 23

The structures of anyone of claims 1, 2, or 3 in which said graphics memory circuits include read only memory.

Claim 26

The device of claim 18 including a pixel size decoder producing outputs indicating the desired propagation of said carry signals in response to the contents of a pixel size register indicating the number of pixels in a data word.

Claim 27

The device of claim 19 in which said pixel size decoder produces two outputs carrying a binary indication of the desired propagation.

Claim 28

The device of claim 18 in which said control circuits include gates that control said propagation in response to the contents of a pixel size register indicating the number of pixels in a data word.

Claim 29

The device of claim 18 including a carry bus encoder producing a carry bus output in response to the contents of a pixel size register indicating the number of pixels in a data word and the carry signals from said subunits.

Claim 30

The device of claim 18 in which there are a binary multiple of subunits.

Claim 31

The device of claim 18 in which there are 16 leads in each bus, there are four subunits each connected to four leads of each bus, and there are three gates in said control circuits that connect the carry signals from three subunits to three subunits.

Claim 34

The device of claim 25 in which said said saturation unit includes an array of select circuits, one for each signal on said input and output buses, receiving said control bus of signals to produce an expanded carry bus of data signals.

Claim 35

The device of claim 25 in which said saturation unit includes a bus selector selecting between said processed set of pixels on said input bus and said replacement data signals to produce said second set of pixels in response to said control bus of signals.

Claim 36

The device of claim 27 including an add/subtract signal applied to said bus selector to invert the values of said control bus of signals.

Claim 37

The device of claim 28 in which pixels on said input and output buses are aligned with one another, the input and output buses have 16 leads, and there is associated with each lead a 1 of 3 select circuit of gates and a bus select circuit of gates, said control signals are carry signals, said nonlinear operation includes an arithmetic addition and an arithmetic substration, and said replacement data signals are saturation data signals.

Claim 40

The device of claim 30 in which said certain values are all logic level 1s and all logic level 0s.

Claim 41

The device of claim 30 in which said arithmetic logic unit includes control circuits for selectively connecting the carry signals between subunits based upon the contents of a pixel size register.

Claim 42

The device of claim 30 in which there are 4 subunits selectively operating as 1 unit, 2 subunits and 4 subunits.

Claim 43

The device of claim 30 in which said saturation unit includes selector gates to produce said resultant word of pixels from said output word and said carry signals.