US5231544A
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Method and apparatus for signal detection in a magnetic recording and reproducing apparatus
Assignee: Hitachi Ltd
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Filing: 1991-01-28
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Granted: 1993-07-27
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Expires: 2011-01-28
Abstract
Abstract A signal detection circuit of a magnetic recording and reproducing apparatus generates a clock signal synchronized with peaks of a reproduced signal read from a magnetic recording medium on which data have been recorded by a (d, k) run-length code, and determines "1" or "0" with respect to a discrimination threshold based on an absolute value of a peak of the reproduced waveform at a timing synchronized with the clock signal. The signal detection circuit comprises a quantizer for quantizing the reproduced signal in synchronism with the clock signal to produce a quantized signal, a multi-stage shift register for delaying the clock signal in synchronism with the clock signal, and threshold generation means for comparing the quantized signal supplied from the final stage of the multi-stage shift register and the quantized signal representing the current threshold to dynamically generate a new relevant threshold in accordance with the difference in the comparison.
Inventors
- 👤 Hiromi Matsushige
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:55
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
295 words
A signal detection circuit of a recording and reproducing apparatus for generating a clock signal synchronized with peaks of a reproduced signal read from a recording medium and determining "1" or "0" based on an absolute value of the peak of the reproduced waveform at a timing synchronized with the clock signal, comprising: quantizing means for quantizing the reproduced signal in synchronism with the clock signal to produce a quantized signal; a multi-stage shift register for delaying the quantized signal in synchronism with the clock signal; reference signal generation means for comparing the quantized signal supplied from a final stage of the multi-stage shift register and a quantized signal representing a current reference, generating a predetermined value determined by the quantized signal supplied from the final stage of the shift register as a new reference when the quantized signal supplied from the final stage of the shift register is larger or smaller than the quantized signal representing the current reference, and maintaining the current reference when the quantized signal supplied from the final stage of the shift register is equal to the quantized signal representing the current reference; operation means for adding the reference to the quantized signal supplied from the final stage of the shift register and subtracting the quantized signal supplied from the final stage of the shift register from the reference; and detection means for comparing the quantized signals supplied from the respective stages of the shift register with the added and subtracted quantized signals supplied from the operation means by a detection logic for data pattern "1" in accordance with a (d, k) run-length code, and detecting "1" by the detection logic for the data pattern "1" in accordance with the (d, k) run-length code based on the result of comparison.
Claim 2
Dependent Claim
295 words
A signal detection circuit of a recording and reproducing apparatus for generating a clock signal synchronized with peaks of a reproduced signal read from a recording medium and determining "1" or "0" based on an absolute value of the peak of the reproduced waveform at a timing synchronized with the clock signal, comprising: quantizing means for quantizing the reproduced signal in synchronism with the clock signal to produce a quantized signal; a multi-stage shift register for delaying the quantized signal in synchronism with the clock signal; reference signal generation means for comparing the quantized signal supplied from a final stage of the multi-stage shift register and a quantized signal representing a current reference, generating a predetermined value determined by the quantized signal supplied from the final stage of the shift register as a new reference when the quantized signal supplied from the final stage of the shift register is larger or smaller than the quantized signal representing the current reference, and maintaining the current reference when the quantized signal supplied from the final stage of the shift register is equal to the quantized signal representing the current reference; operation means for adding the reference to the quantized signal supplied from the final stage of the shift register and subtracting the quantized signal supplied from the final stage of the shift register from the reference; and detection means for comparing the quantized signals supplied from the respective stages of the shift register with the added and subtracted quantized signals supplied from the operation means by a detection logic for data pattern "1" in accordance with a (d, k) run-length code, and detecting "1" by the detection logic for the data pattern "1" in accordance with the (d, k) run-length code based on the result of comparison.
Claim 3
Dependent Claim
119 words
A signal detection circuit according to claim 1 wherein said reference signal generation means compares the quantized signal supplied from the final stage of the shift register with 1/n of the quantized signal representing the current reference, generates the quantized signal supplied from the final stage of the shift register plus or less a predetermined value as a new reference when the quantized signal supplied from the final stage of the shift register is larger or smaller than the 1/n of the quantized signal representing the current reference, and maintaining the current reference when the quantized signal supplied from the final stage of the shift register is equal to the 1/n of the quantized signal representing the current reference.
Claim 4
Dependent Claim
241 words
A digital signal detection method in a recording and reproducing apparatus for generating a clock signal synchronized with peaks of a reproduced signal read from a recording medium and determining "1" or "0" with respect to a reference based on an absolute value of the peak of the reproduced waveform at a timing synchronized with the clock signal, comprising the steps of: quantizing the reproduced signal in synchronism with the clock signal to produce a quantized signal; delaying the quantized signal by a plurality of stages in synchronism with the clock signal; comparing the quantized signal supplied from a final stage of the multi-stage delay and a quantized signal representing a current reference to generate a new reference in accordance with a difference between the quantized signal supplied from the final stage and the quantized signal representing the current reference; adding the reference to the quantized signal supplied from the final stage of the shift delay and subtracting the quantized signal supplied from the final stage of the shift delay from the reference; and comparing the quantized signals supplied from the respective stages of the shift delay with the added and subtracted quantized signals supplied from the addition/subtraction step by a detection logic for data pattern "1" in accordance with a (d, k) run-length code, and detecting "1" by the detection logic for the data pattern "1" in accordance with the (d, k) run-length code based on the result of comparison.
Claim 5
Dependent Claim
241 words
A digital signal detection method in a recording and reproducing apparatus for generating a clock signal synchronized with peaks of a reproduced signal read from a recording medium and determining "1" or "0" with respect to a reference based on an absolute value of the peak of the reproduced waveform at a timing synchronized with the clock signal, comprising the steps of: quantizing the reproduced signal in synchronism with the clock signal to produce a quantized signal; delaying the quantized signal by a plurality of stages in synchronism with the clock signal; comparing the quantized signal supplied from a final stage of the multi-stage delay and a quantized signal representing a current reference to generate a new reference in accordance with a difference between the quantized signal supplied from the final stage and the quantized signal representing the current reference; adding the reference to the quantized signal supplied from the final stage of the shift delay and subtracting the quantized signal supplied from the final stage of the shift delay from the reference; and comparing the quantized signals supplied from the respective stages of the shift delay with the added and subtracted quantized signals supplied from the addition/subtraction step by a detection logic for data pattern "1" in accordance with a (d, k) run-length code, and detecting "1" by the detection logic for the data pattern "1" in accordance with the (d, k) run-length code based on the result of comparison.
Claim 6
Dependent Claim
115 words
A signal detection method according to claim 3 wherein said reference signal generation step compares the quantized signal supplied from the final stage of the shift delay with 1/n of the quantized signal representing the current reference, generates the quantized signal supplied from the final stage of the shift delay plus a predetermined value as a new reference when the quantized signal supplied from the final stage of the shift delay is different from the 1/n of the quantized signal representing the current reference, and maintaining the current reference when the quantized signal supplied from the final stage of the shift delay is equal to the 1/n of the quantized signal representing the current reference.
Claim 7
Dependent Claim
284 words
A signal detection circuit of a magnetic recording and reproducing apparatus for generating a clock signal synchronized with peaks of a reproduced signal read from a magnetic recording medium and determining "1" or "0" based on an absolute value of the peak of the reproduced waveform at a timing synchronized with the clock signal, comprising: quantizing means for quantizing the reproduced signal in synchronism with the clock signal to produce a quantized signal; a multi-stage shift register for delaying the quantized signal in synchronism with the clock signal; reference signal generation means for comparing the quantized signal supplied from a final stage of the multi-stage shift register and a quantized signal representing a current reference, generating a predetermined value determined by the quantized signal supplied from the final stage of the shift register plus or minus a predetermined value, in proportion to a difference calculated in the comparison, as a new reference when the quantized signal supplied from the final stage of the shift register is larger or smaller than the quantized signal representing the current reference; operation means for adding the reference to the quantized signal supplied from the final stage of the shift register and subtracting the quantized signal supplied from the final stage of the shift register from the reference; and detection means for comparing the quantized signals supplied from the respective stages of the shift register with the added and subtracted quantized signals supplied from the operation means by a detection logic for data pattern "1" in accordance with a (d, k) run-length code, and detecting "1" by the detection logic for the data pattern "1" in accordance with the (d, k) run-length code based on the result of comparison.
Claim 8
Dependent Claim
284 words
A signal detection circuit of a magnetic recording and reproducing apparatus for generating a clock signal synchronized with peaks of a reproduced signal read from a magnetic recording medium and determining "1" or "0" based on an absolute value of the peak of the reproduced waveform at a timing synchronized with the clock signal, comprising: quantizing means for quantizing the reproduced signal in synchronism with the clock signal to produce a quantized signal; a multi-stage shift register for delaying the quantized signal in synchronism with the clock signal; reference signal generation means for comparing the quantized signal supplied from a final stage of the multi-stage shift register and a quantized signal representing a current reference, generating a predetermined value determined by the quantized signal supplied from the final stage of the shift register plus or minus a predetermined value, in proportion to a difference calculated in the comparison, as a new reference when the quantized signal supplied from the final stage of the shift register is larger or smaller than the quantized signal representing the current reference; operation means for adding the reference to the quantized signal supplied from the final stage of the shift register and subtracting the quantized signal supplied from the final stage of the shift register from the reference; and detection means for comparing the quantized signals supplied from the respective stages of the shift register with the added and subtracted quantized signals supplied from the operation means by a detection logic for data pattern "1" in accordance with a (d, k) run-length code, and detecting "1" by the detection logic for the data pattern "1" in accordance with the (d, k) run-length code based on the result of comparison.
Claim 9
Dependent Claim
128 words
A signal detection circuit according to claim 5 wherein said reference signal generation means compares the quantized signal supplied from the final stage of the shift register with a product of the quantized signal representing the current reference and a predetermined coefficient, generates the quantized signal supplied from the final stage of the shift register plus or minus a predetermined value as a new reference when the quantized signal supplied from the final stage of the shift register is different from the product of the quantized signal representing the current reference and the coefficient, and maintaining the current reference when the quantized signal supplied from the final stage of the shift register is equal to the product of the quanitzed signal representing the current reference and the coefficient.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-26 | 1997-01-25 | 1997-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-26 | 2001-01-25 | 2001-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-26 | 2005-01-25 | 2005-07-27 | $7700.00 | Window Closed / Lapsed |