US5231053A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of forming a tri-layer titanium coating for an aluminum layer of a semiconductor device
Assignee: Intel Corp
•
Filing: 1991-10-15
•
Granted: 1993-07-27
•
Expires: 2011-10-15
Abstract
Abstract A tri-layer titanium coating for an aluminum layer of a semiconductor device. An aluminum layer used for interconnecting individual devices of an integrated circuit is formed on a semiconductor material. A first titanium nitride layer is deposited on the aluminum layer. A titanium layer is deposited on the first titanium nitride layer. A second titanium nitride layer is then deposited on the titanium layer. The tri-layer titanium coating prevents the formation of Al 2 O 3 and AlF 3 during the etching of a via hole in an intermetal dielectric layer deposited above the second titanium nitride layer.
Inventors
- 👤 Melton C. Bost
- 👤 Simon Yang
- 👤 Yeochung Yen
- 👤 Jim Baldo
- 👤 Barbara Greenebaum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:23
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/038; H10W20/071; H10W20/081; H10W20/083; H10W20/40; H10W20/41; H10W20/425; H10W20/44; H10W20/4473; H10W20/0375; Y; Y10; Y10S; Y10S257/00; Y10S257/913; Y10S257/915
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
130 words
A process for etching a via hole in an intermetal dielectric layer of a semiconductor integrated circuit comprising the steps of: forming an aluminum layer for interconnecting individual devices formed on a semiconductor material; forming a first TiN layer on said aluminum layer; forming a Ti layer on said first TiN layer; forming a second TiN layer on said Ti layer; forming an intermetal dielectric layer on said second TiN layer; forming a photoresist layer on said intermetal dielectric layer; masking, exposing and developing said photoresist layer to define at least one location in said photoresist layer where said via hole will be fabricated; and etching said intermetal dielectric layer at said location until said Ti layer is substantially revealed to form said via hole in said intermetal dielectric layer.
Claim 2
Dependent Claim
130 words
A process for etching a via hole in an intermetal dielectric layer of a semiconductor integrated circuit comprising the steps of: forming an aluminum layer for interconnecting individual devices formed on a semiconductor material; forming a first TiN layer on said aluminum layer; forming a Ti layer on said first TiN layer; forming a second TiN layer on said Ti layer; forming an intermetal dielectric layer on said second TiN layer; forming a photoresist layer on said intermetal dielectric layer; masking, exposing and developing said photoresist layer to define at least one location in said photoresist layer where said via hole will be fabricated; and etching said intermetal dielectric layer at said location until said Ti layer is substantially revealed to form said via hole in said intermetal dielectric layer.
Claim 3
Dependent Claim
33 words
The process as defined in claim 1 further comprising the steps of: forming a tungsten plug in said via hole; forming an aluminum layer on said intermetal dielectric and on said tungsten plug.
Claim 4
Dependent Claim
20 words
The process defined in claim 1 wherein said first TiN layer is formed to a thickness of approximately 450 Å.
Claim 5
Dependent Claim
19 words
The process defined in claim 1 wherein said Ti layer is formed to a thickness of approximately 1000 Å.
Claim 6
Dependent Claim
20 words
The process defined in claim 1 wherein said second TiN layer is formed to a thickness of approximately 450 Å.
Claim 7
Dependent Claim
173 words
A process for etching a via hole in a dielectric layer of a semiconductor integrated circuit formed on a semiconductor substrate comprising the steps of: forming an aluminum layer on said semiconductor substrate; forming a first TiN layer on said aluminum layer wherein said first TiN layer is formed thick enough to ensure no interaction between said aluminum layer and a subsequently formed Ti layer; forming a Ti layer on said first TiN layer wherein said Ti layer is formed thick enough to shunt voids which may develop in said aluminum layer; forming a second TiN layer on said Ti layer, wherein said second TiN layer is formed thick enough to act as an anti-reflective coating; forming a dielectric layer over said second TiN layer; forming a masking layer over said dielectric layer; defining at least one location in said masking layer where said via hole will be formed; and etching said dielectric layer at said location until said Ti layer is substantially revealed to form said via hole in said dielectric layer.
Claim 8
Dependent Claim
173 words
A process for etching a via hole in a dielectric layer of a semiconductor integrated circuit formed on a semiconductor substrate comprising the steps of: forming an aluminum layer on said semiconductor substrate; forming a first TiN layer on said aluminum layer wherein said first TiN layer is formed thick enough to ensure no interaction between said aluminum layer and a subsequently formed Ti layer; forming a Ti layer on said first TiN layer wherein said Ti layer is formed thick enough to shunt voids which may develop in said aluminum layer; forming a second TiN layer on said Ti layer, wherein said second TiN layer is formed thick enough to act as an anti-reflective coating; forming a dielectric layer over said second TiN layer; forming a masking layer over said dielectric layer; defining at least one location in said masking layer where said via hole will be formed; and etching said dielectric layer at said location until said Ti layer is substantially revealed to form said via hole in said dielectric layer.
Claim 9
Dependent Claim
168 words
A process for etching a via hole in a dielectric layer of a semiconductor integrated circuit formed on a semiconductor substrate comprising the steps of: forming a multilayer metal layer on said semiconductor substrate with a method comprising the steps of: forming an aluminum layer on said substrate; forming a first TiN layer on said aluminum layer; forming a Ti layer on said first TiN layer; forming a second TiN layer on said Ti layer; patterning said multilayer metal layer into a plurality of multilayer metal lines, said multilayer metal lines electrically interconnecting various devices formed on said semiconductor substrate; forming a dielectric layer over said multilayer metal lines; forming a masking layer over said dielectric layer; patterning said masking layer to define a location over one of said multilayer metal lines where said via hole will be formed; and etching said dielectric layer at said location until said Ti layer of said multilayer metal line is substantially revealed to form said via hole in said dielectric layer.
Claim 10
Dependent Claim
168 words
A process for etching a via hole in a dielectric layer of a semiconductor integrated circuit formed on a semiconductor substrate comprising the steps of: forming a multilayer metal layer on said semiconductor substrate with a method comprising the steps of: forming an aluminum layer on said substrate; forming a first TiN layer on said aluminum layer; forming a Ti layer on said first TiN layer; forming a second TiN layer on said Ti layer; patterning said multilayer metal layer into a plurality of multilayer metal lines, said multilayer metal lines electrically interconnecting various devices formed on said semiconductor substrate; forming a dielectric layer over said multilayer metal lines; forming a masking layer over said dielectric layer; patterning said masking layer to define a location over one of said multilayer metal lines where said via hole will be formed; and etching said dielectric layer at said location until said Ti layer of said multilayer metal line is substantially revealed to form said via hole in said dielectric layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-26 | 1997-01-25 | 1997-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-26 | 2001-01-25 | 2001-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-26 | 2005-01-25 | 2005-07-27 | $7700.00 | Window Closed / Lapsed |