Solid state memory modules and memory devices including such modules

Claim 2

A memory module comprising an interconnection substrate and a plurality of semi-conductor memory chips carried by said substrate, all said chips having a same elongated shape with two end portions and two lateral sides directed along the direction of elongation and each of said chips having output connections located at said end portions, wherein at least two of said chips are mutually stacked and are mutually crossed so that the output connections of an upper one of said two chips are beyond said lateral surfaces of the chip which is located under said upper one of said two chips in the stack, wherein the output connections of each of said two chips are located on a major surface of the respective chip which is farther from the interconnection substrate, and wherein said output connections are electrically connected to conductive paths on said interconnection substrate by bonded flexible wires.

Claim 3

A memory module comprising an interconnection substrate and a plurality of semi-conductor memory chips carried by said substrate, wherein all said chips having a same elongated shape, wherein each of said chips has output connections located at end portions thereof, wherein at least two of said chips are mutually stacked and are mutually crossed so that the output connections of an upper one of said two chips are beyond a periphery of the chip which is located under said upper one of said two chips in the stack, wherein the output connections of each of said two chips are located on a major surface of the chip which is farther from the interconnection substrate, and are electrically connected to conductive paths on said interconnection substrate by bonded flexible wires, wherein a lowest one of said chips in said stack is bonded to the interconnection substrate, and wherein supporting blocks are located under cantilevered ends of each of said chips other than said lowest chip.

Claim 4

A memory module comprising an interconnection substrate and a plurality of semi-conductor memory chips carried by said substrate, wherein all said chips having a same elongated shape, wherein each of said chips has output connections located at end portions thereof, wherein at least two of said chips are mutually stacked and are mutually crossed so that the output connections of an upper one of said two chips are beyond a periphery of the chip which is located under said upper one of said two chips in the stack, wherein the output connections of each of said two chips are located on a major surface of the chip which is farther from the interconnection substrate, and are electrically connected to conductive paths on said interconnection substrate by bonded flexible wires, wherein a lowest one of said chips in said stack is bonded to the interconnection substrate, and wherein supporting blocks are located under cantilevered ends of each of said chips other than said lowest chip.

Claim 5

Module according to claim 1, comprising three said chips at mutual angles of 60°.

Claim 6

Module according to claim 1, further comprising small size auxiliary components placed between end portions of said two mutually crossed chips.

Claim 7

Module according to claim 4, wherein said auxiliary components are capacitors and integrated logic circuits.

Claim 8

Memory module comprising: an interconnection substrate; a first set of two mutually parallel identical semi-conductor memory chips bonded to said substrate, having an elongated shape and having output connections located at the ends thereof and on their surface away from said interconnection substrate; and a second set of two mutually parallel semi-conductor memory chips which are identical to the chips of the first set and are crossed at right angle with the chips of said first set, having their output connections located on their surface away from said interconnection substrate, said output connections of all said chips being electrically connected to said interconnection substrate by bonded wires.

Claim 9

Memory module comprising: an interconnection substrate; a first set of two mutually parallel identical semi-conductor memory chips bonded to said substrate, having an elongated shape and having output connections located at the ends thereof and on their surface away from said interconnection substrate; and a second set of two mutually parallel semi-conductor memory chips which are identical to the chips of the first set and are crossed at right angle with the chips of said first set, having their output connections located on their surface away from said interconnection substrate, said output connections of all said chips being electrically connected to said interconnection substrate by bonded wires.

Claim 10

Module according to claim 6, wherein said first set and said second set constitute a first unit and said module further comprises an additional unit consisting of two additional sets identical to the sets of the first unit, superposed to the first unit and supporting blocks located under cantilevered ends of chips of said additional unit.

Claim 11

Module according to claim 6, wherein said substrate has two major faces and each said major face carries at least one said first set and one said second set.

Claim 12

Module according to claim 7 wherein said substrate has two major surfaces and each said major face carries at least one said first unit and one said additional unit.

Claim 13

Module according to claim 1, further comprising an insulating support having a major surface carrying conductive paths constituting a bus, wherein a plurality of said interconnection substrates each having at least two said chips are bonded on said insulating support, said bus passing under a plurality of said substrates which are each provided with means for electrical connection with the bus.