Method of and apparatus for assigning logic gates to a plurality of hardware components

Claim 1

A method of assigning a plurality of logic function elements arranged in a hierarchical structure representative of connection relations among a plurality of logic gates to a plurality of hardware components, to be used for forming a high speed logic apparatus, each of which apparatus components can accommodate a predetermined maximum allowable number of logic gates and each of which can carry a predetermined maximum allowable number of input and output pins, each of said logic functions elements including at least one logic gate, the method comprising the steps of: assigning to one of said hardware components(1) those logic function elements which include logic gates the number of which is larger than a first condition value and is smaller than a maximum allowable number of logic gates which one of said hardware components can accommodate and (2) those logic function elements which include logic gates the number of which is smaller than a second condition value; assigning to one of said hardware components those of next lower level logic function elements to the remaining logic function elements which include logic gates the number of which is smaller than said second condition value; and repeating the first-mentioned step for those of next lower level logic function elements to said remaining logic function elements which include logic gates the number of which is not smaller than said second condition value to thereby assign logic function elements to the hardware components to be used for forming a high speed logic apparatus.

Claim 2

A method of assigning a plurality of logic function elements arranged in a hierarchical structure representative of connection relations among a plurality of logic gates to a plurality of hardware components, to be used for forming a high speed logic apparatus, each of which apparatus components can accommodate a predetermined maximum allowable number of logic gates and each of which can carry a predetermined maximum allowable number of input and output pins, each of said logic functions elements including at least one logic gate, the method comprising the steps of: assigning to one of said hardware components(1) those logic function elements which include logic gates the number of which is larger than a first condition value and is smaller than a maximum allowable number of logic gates which one of said hardware components can accommodate and (2) those logic function elements which include logic gates the number of which is smaller than a second condition value; assigning to one of said hardware components those of next lower level logic function elements to the remaining logic function elements which include logic gates the number of which is smaller than said second condition value; and repeating the first-mentioned step for those of next lower level logic function elements to said remaining logic function elements which include logic gates the number of which is not smaller than said second condition value to thereby assign logic function elements to the hardware components to be used for forming a high speed logic apparatus.

Claim 6

A method of physically assigning a plurality of logic gates to a plurality of hardware components to be used for forming a high speed logic apparatus, said logic gates being logically arranged in a first hierarchical structure in terms of a cluster of logical functions in which at least one of a plurality of logic function elements at on level accommodates at least one logic function element at a lower level, and in which each of said logic gates is included in one of said logic function elements, the method comprising the steps of: selecting a number of logic function elements as to-be-processed function elements among said logic function elements in said first hierarchical structure on the basis of the number of said plurality of hardware components and a maximum allowable number of gates each of said hardware components can accommodate; classifying said selected to-be-processed function elements in said first hierarchical structure into at least two elements groups on the basis of strengths of connection among said to-be-processed function elements, a maximum allowable number of pins each of said hardware components can carry, and said maximum allowable number of gates each of said hardware components can accommodate; and rearranging said selected to-be-processed function elements in said first hierarchical structure into a second hierarchical structure in terms of a cluster of logical functions in which all of said to-be-processed function elements are partitioned into said plurality of element groups so that each of said element groups corresponds of those of said logic function elements which are physically assignable to a different one of said hardware components to thereby assign logic function elements to the hardware components to be used for forming a high speed logic apparatus.

Claim 7

A method of physically assigning a plurality of logic gates to a plurality of hardware components to be used for forming a high speed logic apparatus, said logic gates being logically arranged in a first hierarchical structure in terms of a cluster of logical functions in which at least one of a plurality of logic function elements at on level accommodates at least one logic function element at a lower level, and in which each of said logic gates is included in one of said logic function elements, the method comprising the steps of: selecting a number of logic function elements as to-be-processed function elements among said logic function elements in said first hierarchical structure on the basis of the number of said plurality of hardware components and a maximum allowable number of gates each of said hardware components can accommodate; classifying said selected to-be-processed function elements in said first hierarchical structure into at least two elements groups on the basis of strengths of connection among said to-be-processed function elements, a maximum allowable number of pins each of said hardware components can carry, and said maximum allowable number of gates each of said hardware components can accommodate; and rearranging said selected to-be-processed function elements in said first hierarchical structure into a second hierarchical structure in terms of a cluster of logical functions in which all of said to-be-processed function elements are partitioned into said plurality of element groups so that each of said element groups corresponds of those of said logic function elements which are physically assignable to a different one of said hardware components to thereby assign logic function elements to the hardware components to be used for forming a high speed logic apparatus.

Claim 9

An apparatus for physically assigning a plurality of logic gates to a plurality of hardware components to be used for forming a high speed logic apparatus, said logic gates being logically arranged in a first hierarchical structure in terms of a cluster of logical functions to constitute a high speed logic operation apparatus in which at least one of a plurality of logic function elements at one level accommodates at least one logic function element at a lower level, and in which each of said logic gates is includes in one of said logic function elements, the apparatus comprising: a first memory for storing therein at least initial data with respect to hierarchical descriptions of logic operation of and hardware specification of said high speed logic operation apparatus, the data on said hardware specification including data with respect to a number of said plurality of hardware components, a maximum allowable number of gates each of said hardware component can accommodate, strengths of connection among said function elements, and a maximum allowable number of pins each of said hardware components can carry; an input section for receiving said initial data from said first memory and for buffering the initial data; means coupled to said input section for selecting a number of logic function elements as to-be-processed function elements among said logic function elements in said first hierarchical structure on the basis of the number of said plurality of hardware components and the maximum allowable number of gates each of said hardware components can accommodate; means coupled to said input section and said selecting means for classifying said selected to-be-processed function elements in said first hierarchical structure into at least two element groups on the basis of strengths of connection among said to-be-processed function elements, a maximum allowable number of pins each of said hardware. components can carry, and said maximum allowable number of gates each of said hardware components can accommodate; means coupled to said classifying means for rearranging said selected to-be-processed function elements in said first hierarchical structure into a second hierarchical structure in terms of a cluster of logical functions in which all of said to-be-processed function elements are partitioned into said plurality of element groups so that each of said element groups corresponds to those of said logic function elements which are physically assignable to a different one of said hardware components; an output section for receiving data from said rearranging means with respect to said second hierarchical structure and for buffering the received data; and a second memory for storing therein said received data with respect to said second hierarchical structure to thereby assign logic function elements to the hardware components to be used for forming a high speed logic apparatus.

Claim 10

An apparatus for physically assigning a plurality of logic gates to a plurality of hardware components to be used for forming a high speed logic apparatus, said logic gates being logically arranged in a first hierarchical structure in terms of a cluster of logical functions to constitute a high speed logic operation apparatus in which at least one of a plurality of logic function elements at one level accommodates at least one logic function element at a lower level, and in which each of said logic gates is includes in one of said logic function elements, the apparatus comprising: a first memory for storing therein at least initial data with respect to hierarchical descriptions of logic operation of and hardware specification of said high speed logic operation apparatus, the data on said hardware specification including data with respect to a number of said plurality of hardware components, a maximum allowable number of gates each of said hardware component can accommodate, strengths of connection among said function elements, and a maximum allowable number of pins each of said hardware components can carry; an input section for receiving said initial data from said first memory and for buffering the initial data; means coupled to said input section for selecting a number of logic function elements as to-be-processed function elements among said logic function elements in said first hierarchical structure on the basis of the number of said plurality of hardware components and the maximum allowable number of gates each of said hardware components can accommodate; means coupled to said input section and said selecting means for classifying said selected to-be-processed function elements in said first hierarchical structure into at least two element groups on the basis of strengths of connection among said to-be-processed function elements, a maximum allowable number of pins each of said hardware. components can carry, and said maximum allowable number of gates each of said hardware components can accommodate; means coupled to said classifying means for rearranging said selected to-be-processed function elements in said first hierarchical structure into a second hierarchical structure in terms of a cluster of logical functions in which all of said to-be-processed function elements are partitioned into said plurality of element groups so that each of said element groups corresponds to those of said logic function elements which are physically assignable to a different one of said hardware components; an output section for receiving data from said rearranging means with respect to said second hierarchical structure and for buffering the received data; and a second memory for storing therein said received data with respect to said second hierarchical structure to thereby assign logic function elements to the hardware components to be used for forming a high speed logic apparatus.