Patent US6347952B1 successfully refreshed from Google Patents.
US5229772A
Expired / Lapsed
US
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Ratiometric ADC with pulse width modulated output for wide temperature range applications
Assignee: Texas Instruments Inc
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Filing: 1992-02-03
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Granted: 1993-07-20
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Expires: 2012-02-03
Abstract
Abstract An analog-to-digital converter (ADC) includes a capacitor array coupled to switches, an integrator stage connected to the switchable capacitors and a comparator stage connected to the output of the integrator stage. Means coupled to the comparator stage include a feedback loop to effectuate switching reference signals of opposite polarity for use during respective phases of operation of the ADC. The values of the capacitors can be programmed by the user of the ADC and switched to provide a desired total capacitance. For any fixed ratio of the input voltage to reference voltage, the duty cycle remains constant over a wide range of temperatures. Multiple stages afford large effective capacitor ratios with a small range of actual capacitance values and enable a reduction in silicon chip area for an ADC integrated circuit.
Inventors
- 👤 Michael M. Hanlon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:15
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0619; H03M1/12; H03M1/50; H03M1/504
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
198 words
An analog-to-digital converter for providing a constant duty cycle that is a constant ratio of input voltage divided by reference voltage over a relatively large range of temperature comprising: an input circuit for receiving reference voltage and input voltage signals; means for providing an input voltage signal to said input circuit; a source of negative and positive reference voltage signals; switching means coupled to said source for selectively supplying reference voltage signals of first and second polarities respectively to said input circuit; a clock generator for providing alternating phases of operation of said converter; a single integrator stage coupled to said input circuit for receiving said reference voltage and input voltage signals; a capacitor array coupled between said input circuit and said integrator stage; a comparator stage coupled to said integrator stage for comparing the output signal from said integrator to trip voltages; logic means coupled to the output of said comparator means and to said switching means that is coupled to said source for actuating said switching means to change said reference signals alternately between negative and positive polarities so that said duty cycle is defined by two phases of negative going and positive going signal waveforms.
Claim 2
Dependent Claim
198 words
An analog-to-digital converter for providing a constant duty cycle that is a constant ratio of input voltage divided by reference voltage over a relatively large range of temperature comprising: an input circuit for receiving reference voltage and input voltage signals; means for providing an input voltage signal to said input circuit; a source of negative and positive reference voltage signals; switching means coupled to said source for selectively supplying reference voltage signals of first and second polarities respectively to said input circuit; a clock generator for providing alternating phases of operation of said converter; a single integrator stage coupled to said input circuit for receiving said reference voltage and input voltage signals; a capacitor array coupled between said input circuit and said integrator stage; a comparator stage coupled to said integrator stage for comparing the output signal from said integrator to trip voltages; logic means coupled to the output of said comparator means and to said switching means that is coupled to said source for actuating said switching means to change said reference signals alternately between negative and positive polarities so that said duty cycle is defined by two phases of negative going and positive going signal waveforms.
Claim 3
Dependent Claim
93 words
An analog-to-digital converter as in claim 1, including first and second switches for connecting said input circuit to said reference signal switching means and to said input voltage signal providing means respectively; a summing junction to which said input voltage signal and said reference signal are applied; first and second comparators for receiving a summed signal from said junction during said first and second phases of operation respectively; a third switch coupled to a summing junction of said capacitor array; and a fourth switch coupled to said capacitor array and said integrator stage.
Claim 4
Dependent Claim
26 words
An analog-to-digital converter as in claim 2, including a clock generator for controlling said reference signal switching means and said first, second, third and fourth switches.
Claim 5
Dependent Claim
22 words
An analog-to-digital converter as in claim 3, wherein said clock generator is a two phase clock for providing alternating phases of operation.
Claim 6
Dependent Claim
62 words
An analog-to-digital converter as in claim 4, wherein said switching means is connected to said source of reference voltage of negative polarity during a first phase of the duty cycle of said converter, so that the current produced by said negative voltage is greater than the current produced by an input voltage signal, whereby the output of said integrator is increased accordingly.
Claim 7
Dependent Claim
62 words
An analog-to-digital converter as in claim 4, wherein said switching means is connected to a source of reference voltage of positive polarity during a second phase of the duty cycle of said converter, so that the current produced by said positive voltage is less than the current produced by an input voltage signal, whereby the output of said integrator is decreased accordingly.
Claim 8
Dependent Claim
74 words
An analog-to-digital converter as in claim 1, wherein said input circuit includes first and second unity gain amplifiers, said first amplifier being connected between a first switch of said switching means coupled to said reference signal source and a first capacitor of said capacitor array, said second amplifier being connected between a second switch of said switching means coupled to said input voltage signal providing means and a second capacitor of said capacitor array.
Claim 9
Dependent Claim
33 words
An analog-to-digital converter as in claim 7, wherein said capacitor array comprises a third capacitor, said third capacitor being connected at a summing junction, and to the input circuit of said integrator stage.
Claim 10
Dependent Claim
31 words
An analog-to-digital converter as in claim 8, wherein said integrator stage comprises an operational amplifier and a capacitor for processing the signal provided to said input circuit of said integrator stage.
Claim 11
Dependent Claim
19 words
An analog-to-digital converter as in claim 1, including feedback means coupled between said actuating means and said switching means.
Claim 12
Dependent Claim
15 words
An analog-to-digital converter as in claim 1, wherein said actuating means comprises a logic circuit.
Claim 13
Dependent Claim
122 words
An analog-to-digital converter comprising: first and second amplifiers; means for applying an input voltage to said first amplifier; a source of reference voltage for providing positive and negative reference signals to said second amplifier; switching means connected between said input voltage applying means, said reference voltage source and said amplifiers; first, second and third capacitors coupled to the output of said amplifiers, said capacitors being connected to a summing junction; an integrator coupled to said summing junction for varying the output voltage of said converter in response to the ratio between the input voltage and reference voltage; logic means coupled to receive a signal representing said voltage ratio, said logic means processing said signal for varying the positions of said switching means.
Claim 14
Dependent Claim
122 words
An analog-to-digital converter comprising: first and second amplifiers; means for applying an input voltage to said first amplifier; a source of reference voltage for providing positive and negative reference signals to said second amplifier; switching means connected between said input voltage applying means, said reference voltage source and said amplifiers; first, second and third capacitors coupled to the output of said amplifiers, said capacitors being connected to a summing junction; an integrator coupled to said summing junction for varying the output voltage of said converter in response to the ratio between the input voltage and reference voltage; logic means coupled to receive a signal representing said voltage ratio, said logic means processing said signal for varying the positions of said switching means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-19 | 1997-01-18 | 1997-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-19 | 2001-01-18 | 2001-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-19 | 2005-01-18 | 2005-07-20 | $7700.00 | Window Closed / Lapsed |