Digital signal processor for executing multichannel processing of analog inputs and outputs

Claim 2

A digital signal processor comprising: a plurality of first external terminals; a plurality of second external terminals; a plurality of analog-to-digital converter circuits coupled to said plurality of first external terminals so that each of said plurality of analog-to-digital converter circuits corresponds to a predetermined one of said first external terminals; a plurality of digital-to-analog converter circuits coupled to said plurality of second external terminals so that each of said plurality of digital-to-analog converter circuits corresponds to a predetermined one of said second external terminals; first selector means for selecting one of said plurality of analog-to-digital converter circuits in accordance with a first selection signal; second selector means for selecting one of said plurality of digital-to-analog converter circuits in accordance with a second selection signal; and a processing unit coupled to said first and second selector means, wherein said processing unit inputs a first digital signal from said selected one of said plurality of analog-to-digital converter circuits and outputs a second digital to said selected one of said plurality of digital-to-analog converter circuits, and said processing unit including, instruction memory means for storing instructions to execute corresponding predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said first selection signal for indicating selection of said one of said plurality of analog-to-digital converter circuits and include said second selection signal for indicating selection of said one of said plurality of digital-to-analog converter circuits, arithmetic logic means for performing addition and subtraction operations in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting first and second sampling clock signals in response to a value set in accordance with an instruction in said instruction memory means, wherein said selected one of said plurality of analog-to-digital converter circuits converts a first analog signal into said first digital signal in accordance with said first sampling clock signal, and wherein said selected one of said plurality of digital-to-analog converter circuits converts said second digital signal into a second analog signal in accordance with said second sampling clock signal.

Claim 3

A digital signal processor according to claim 1, further comprising a first register which stores said first digital signal from said selected one of said plurality of analog-to-digital converter circuits and a second register which stores said second digital signal to be provided to said selected one of said plurality of digital-to-analog circuits.

Claim 4

A digital signal processor according to claim 2, further comprising control means for outputting input and output clock signals in response to said first and second sampling clock signals, wherein said first register is inputted with said first digital signal from said selected one of said plurality of analog-to-digital converter circuits, in accordance with the input clock signal, and wherein said second register outputs said second digital signal to said selected one of said plurality of digital-to-analog converter circuits, in accordance with the output clock signal.

Claim 5

A digital signal processor according to claim 1, wherein said first and second sampling clock signals are out of phase with each other.

Claim 6

A digital signal processor according to claim 1, wherein said digital signal processor is formed on a single semiconductor substrate.

Claim 7

A digital signal processor according to claim 1, wherein said first and second selection signals are two-bit control signals.

Claim 8

A digital signal processor according to claim 1, further comprising a host processor interfaced with said processing unit.

Claim 9

A digital signal processor system comprising: a plurality of first external terminals each of which has a single first external device coupled thereto; a plurality of second external terminals each of which has a single second external device coupled thereto; a plurality of analog-to-digital converter circuits coupled to said plurality of first external terminals so that each of said plurality of analog-to-digital converter circuits corresponds to a predetermined one of said first external terminals; a plurality of digital-to-analog converter circuits coupled to said plurality of second external terminals so that each of said plurality of digital-to-analog converter circuits corresponds to a predetermined one of said second external terminals; first selector means for selecting one of said plurality of analog-to-digital converter circuits in accordance with a first selection signal; second selector means for selecting one of said plurality of digital-to-analog converter circuits in accordance with a second selection signal; and a processing unit coupled to said first and second selector means, wherein said processing unit inputs a first digital signal from said selected one of said plurality of analog-to-digital converter circuits and outputs a second digital signal to said selected one of said plurality of digital-to-analog converter circuits; and said processing unit including, instruction memory means for storing instructions to execute corresponding predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said first selection signal for indicating selection of said one of said plurality of analog-to-digital converter circuits and include said second selection signal for indicating selection of said one of said plurality of digital-to-analog converter circuits, arithmetic logic means for performing addition and subtraction operations in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting first and second sampling clock signals in response to a value set in accordance with an instruction in said instruction memory means, wherein said selected one of said plurality of analog-to-digital converter circuits converts a first analog signal into said first digital signal in accordance with said first sampling clock signal, and wherein said selected one of said plurality of digital-to-analog converter circuits converts said second digital signal into a second analog signal in accordance with said second sampling clock signal.

Claim 10

A digital signal processor system comprising: a plurality of first external terminals each of which has a single first external device coupled thereto; a plurality of second external terminals each of which has a single second external device coupled thereto; a plurality of analog-to-digital converter circuits coupled to said plurality of first external terminals so that each of said plurality of analog-to-digital converter circuits corresponds to a predetermined one of said first external terminals; a plurality of digital-to-analog converter circuits coupled to said plurality of second external terminals so that each of said plurality of digital-to-analog converter circuits corresponds to a predetermined one of said second external terminals; first selector means for selecting one of said plurality of analog-to-digital converter circuits in accordance with a first selection signal; second selector means for selecting one of said plurality of digital-to-analog converter circuits in accordance with a second selection signal; and a processing unit coupled to said first and second selector means, wherein said processing unit inputs a first digital signal from said selected one of said plurality of analog-to-digital converter circuits and outputs a second digital signal to said selected one of said plurality of digital-to-analog converter circuits; and said processing unit including, instruction memory means for storing instructions to execute corresponding predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said first selection signal for indicating selection of said one of said plurality of analog-to-digital converter circuits and include said second selection signal for indicating selection of said one of said plurality of digital-to-analog converter circuits, arithmetic logic means for performing addition and subtraction operations in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting first and second sampling clock signals in response to a value set in accordance with an instruction in said instruction memory means, wherein said selected one of said plurality of analog-to-digital converter circuits converts a first analog signal into said first digital signal in accordance with said first sampling clock signal, and wherein said selected one of said plurality of digital-to-analog converter circuits converts said second digital signal into a second analog signal in accordance with said second sampling clock signal.

Claim 11

A digital signal processor system according to claim 8, wherein said processing unit includes a first register which stores said first digital signal from said selected one of said plurality of analog-to-digital converter circuits and a second register which stores said second digital signal to be provided to said selected one of said plurality of digital-to-analog converter circuits.

Claim 12

A digital signal processor system according to claim 9, wherein said processing unit includes control means for outputting input and output clock signals in response to said first and second sampling clock signals, wherein said first register is inputted with said first digital signal from said selected one of said plurality of analog-to-digital converter circuits, in accordance with the input clock signal, and wherein said second register outputs said second digital signal to said selected one of said plurality of digital-to-analog converter circuits, in accordance with the output clock signal.

Claim 13

A digital signal processor system according to claim 8, wherein said first and second sampling clock signals are out of phase with each other.

Claim 14

A digital signal processor system according to claim 8, wherein said first and second selection signals are two-bit control signals.

Claim 15

A digital signal processor system according to claim 8, further comprising a host processor interfaced with said processing unit.

Claim 16

A digital signal processor comprising: a plurality of first external terminals; a plurality of second external terminals; first selector means coupled to said plurality of first external terminals and for selecting one of said plurality of first external terminals in accordance with a first selection signal; second selector means coupled to said plurality of second external terminals and for selecting one of said plurality of second external terminals in accordance with a second selection signal; an analog-to-digital converter circuit coupled to said first selector means and for converting a first analog signal provided from said one of said plurality of first external terminals into a first digital signal; a digital-to-analog converter circuit coupled to said second selector means and for converting a second digital signal into a second analog signal to be supplied to said selected one of said plurality of second external terminals; and a processing unit coupled to said analog-to-digital and digital-to-analog converter circuits, wherein said processing unit inputs said first digital signal from said analog-to digital converter circuit and outputs said second digital signal to said digital-to-analog converter circuit, and said processing unit including, instruction memory means for storing instructions to execute corresponding predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said first selection signal for indicating selection of one of said plurality of first external terminals and said second selection signal for indicating selection of one of said plurality of second external terminals, arithmetic logic means for performing addition and subtraction operation in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting first and second sampling clock signals in response to a value set in accordance with an instruction in said instruction memory means, wherein said analog-to-digital converter circuit converts said first analog signal into said first digital signal in accordance with the first sampling clock signal, and wherein said digital-to-analog converter circuit converts said second digital signal into said second analog signal in accordance with the second sampling clock signal.

Claim 17

A digital signal processor comprising: a plurality of first external terminals; a plurality of second external terminals; first selector means coupled to said plurality of first external terminals and for selecting one of said plurality of first external terminals in accordance with a first selection signal; second selector means coupled to said plurality of second external terminals and for selecting one of said plurality of second external terminals in accordance with a second selection signal; an analog-to-digital converter circuit coupled to said first selector means and for converting a first analog signal provided from said one of said plurality of first external terminals into a first digital signal; a digital-to-analog converter circuit coupled to said second selector means and for converting a second digital signal into a second analog signal to be supplied to said selected one of said plurality of second external terminals; and a processing unit coupled to said analog-to-digital and digital-to-analog converter circuits, wherein said processing unit inputs said first digital signal from said analog-to digital converter circuit and outputs said second digital signal to said digital-to-analog converter circuit, and said processing unit including, instruction memory means for storing instructions to execute corresponding predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said first selection signal for indicating selection of one of said plurality of first external terminals and said second selection signal for indicating selection of one of said plurality of second external terminals, arithmetic logic means for performing addition and subtraction operation in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting first and second sampling clock signals in response to a value set in accordance with an instruction in said instruction memory means, wherein said analog-to-digital converter circuit converts said first analog signal into said first digital signal in accordance with the first sampling clock signal, and wherein said digital-to-analog converter circuit converts said second digital signal into said second analog signal in accordance with the second sampling clock signal.

Claim 18

A digital signal processor according to claim 14, further comprising a first register which stores said first digital signal from said analog-to-digital converter circuit and a second register which stores said second digital signal to be provided to said digital-to-analog converter circuit.

Claim 19

A digital signal processor according to claim 15, further comprising control means for outputting input and output clock signals in response to said first and second sampling clock signals, wherein said first register is inputted with said first digital signal from said analog-to-digital converter circuit, in accordance with the input clock signal, and wherein said second register outputs said second digital signal to said digital-to-analog converter circuit, in accordance with the output clock signal.

Claim 20

A digital signal processor according to claim 14, wherein said first and second sampling clock signals are out of phase with each other.

Claim 21

A digital signal processor according to claim 14, wherein said digital signal processor is formed on a single semiconductor substrate.

Claim 22

A digital signal processor according to claim 14, wherein said first and second selection signals are two-bit control signals.

Claim 23

A digital signal processor according to claim 14, further comprising a host processor interfaced with said processing unit.

Claim 24

A digital signal processor system comprising: a plurality of first external terminals each of which has a single first external device coupled thereto; a plurality of second external terminals each of which has a single second external device coupled thereto; first selector means coupled to said plurality of first external terminals and for selecting one of said plurality of first external terminals in accordance with a first selection signal; second selector means coupled to said plurality of second external terminals and for selecting one of said plurality of second external terminals in accordance with a second selection signal; an analog-to-digital converter circuit coupled to said first selector means and for converting a first analog signal provided from said selected one of said plurality of first external terminals into a first digital signal; a digital-to-analog converter circuit coupled to said second selector means and for converting a second digital signal into a second analog signal to be supplied to said selected one of said plurality of second external terminals; and a processing unit coupled to said analog-to-digital and digital-to-analog converter circuits, wherein said processing unit inputs said first digital signal from said selected analog-to-digital converter circuit and outputs said second digital signal to said selected digital-to-analog converter circuit, and said processing unit including, instruction memory means for storing instructions to execute predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said first selection signal for indicating selection of said one of said plurality of first external terminals and said second selection signal for indicating selection of said one of said plurality of second external terminals, arithmetic logic means for performing addition and subtraction operations in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting first and second sampling clock signals in response to a value set in accordance with an instruction in said instruction memory means, wherein said analog-to-digital converter circuit converts said first analog signal into said first digital signal in accordance with the first sampling clock signal, and wherein said digital-to-analog converter circuit converts said second digital signal into said second analog signal in accordance with the second sampling clock signal.

Claim 25

A digital signal processor system comprising: a plurality of first external terminals each of which has a single first external device coupled thereto; a plurality of second external terminals each of which has a single second external device coupled thereto; first selector means coupled to said plurality of first external terminals and for selecting one of said plurality of first external terminals in accordance with a first selection signal; second selector means coupled to said plurality of second external terminals and for selecting one of said plurality of second external terminals in accordance with a second selection signal; an analog-to-digital converter circuit coupled to said first selector means and for converting a first analog signal provided from said selected one of said plurality of first external terminals into a first digital signal; a digital-to-analog converter circuit coupled to said second selector means and for converting a second digital signal into a second analog signal to be supplied to said selected one of said plurality of second external terminals; and a processing unit coupled to said analog-to-digital and digital-to-analog converter circuits, wherein said processing unit inputs said first digital signal from said selected analog-to-digital converter circuit and outputs said second digital signal to said selected digital-to-analog converter circuit, and said processing unit including, instruction memory means for storing instructions to execute predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said first selection signal for indicating selection of said one of said plurality of first external terminals and said second selection signal for indicating selection of said one of said plurality of second external terminals, arithmetic logic means for performing addition and subtraction operations in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting first and second sampling clock signals in response to a value set in accordance with an instruction in said instruction memory means, wherein said analog-to-digital converter circuit converts said first analog signal into said first digital signal in accordance with the first sampling clock signal, and wherein said digital-to-analog converter circuit converts said second digital signal into said second analog signal in accordance with the second sampling clock signal.

Claim 26

A digital signal processor system according to claim 21, wherein said processing unit includes a first register which stores said first digital signal from said analog-to-digital converter circuit and a second register which stores said second digital signal to be provided to said digital-to-analog converter circuit.

Claim 27

A digital signal processor system according to claim 22, wherein said processing unit includes control means for outputting input and output clock signals in response to said first and second sampling clock signals, wherein said first register is inputted with said first digital signal from said analog-to-digital converter circuit, in accordance with the input clock signal, and wherein said second register outputs said second digital signal to said digital-to-analog converter circuit, in accordance with the output clock signal.

Claim 28

A digital signal processor system according to claim 21, wherein said first and second sampling clock signals are out of phase with each other.

Claim 29

A digital signal processor system according to claim 21, wherein said first and second selection signals are two-bit control signals.

Claim 30

A digital signal processor system according to claim 21, further comprising a host processor interfaced with said processing unit.

Claim 31

A digital signal processor comprising: a plurality of first external terminals; a plurality of second external terminals; a plurality of analog-to-digital converter circuits coupled to said plurality of first external terminals so that each of said plurality of analog-to-digital converter circuits corresponds to a predetermined one of said first external terminals; a plurality of digital-to-analog converter circuits coupled to said plurality of second external terminals so that each of said plurality of digital-to-analog converter circuits corresponds to a predetermined one of said second external terminals; first selector means for selecting one of said plurality of analog-to-digital converter circuits in accordance with a first selection signal; second selector means for selecting one of said plurality of digital-to-analog converter circuits in accordance with a second selection signal; and a processing unit coupled to said first and second selector means, wherein said processing unit inputs a first digital signal form said selected one of said plurality of analog-to-digital converter circuits and outputs a second digital signal to said selected one of said plurality of digital-to-analog converter circuits, and said processing unit including, instruction memory means for storing instructions to execute corresponding predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said first selection signal for indicating selection of said one of said plurality of analog-to-digital converter circuits and include said second selection signal for indicating selection of said one of said plurality of digital-to-analog converter circuits, arithmetic logic means for performing addition and subtraction operations in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting pairs of first and second sampling clock signals in accordance with an instruction in said instruction memory means, wherein each of said pairs of first and second sampling clock signals is out of phase with the other pairs of first and second sampling clock signals, and wherein said selected one of said plurality of analog-to-digital converter circuits converts a first analog signal into said first digital signal in accordance with the first sampling clock signal of a selected one of said pairs of first and second sampling clock signals, and said selected one of said plurality of digital-to-analog converter circuits converts said second digital signal into a second analog signal in accordance with the second sampling clock signal of said selected one of said pairs of first and second sampling clock signals.

Claim 32

A digital signal processor comprising: a plurality of first external terminals; a plurality of second external terminals; a plurality of analog-to-digital converter circuits coupled to said plurality of first external terminals so that each of said plurality of analog-to-digital converter circuits corresponds to a predetermined one of said first external terminals; a plurality of digital-to-analog converter circuits coupled to said plurality of second external terminals so that each of said plurality of digital-to-analog converter circuits corresponds to a predetermined one of said second external terminals; first selector means for selecting one of said plurality of analog-to-digital converter circuits in accordance with a first selection signal; second selector means for selecting one of said plurality of digital-to-analog converter circuits in accordance with a second selection signal; and a processing unit coupled to said first and second selector means, wherein said processing unit inputs a first digital signal form said selected one of said plurality of analog-to-digital converter circuits and outputs a second digital signal to said selected one of said plurality of digital-to-analog converter circuits, and said processing unit including, instruction memory means for storing instructions to execute corresponding predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said first selection signal for indicating selection of said one of said plurality of analog-to-digital converter circuits and include said second selection signal for indicating selection of said one of said plurality of digital-to-analog converter circuits, arithmetic logic means for performing addition and subtraction operations in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting pairs of first and second sampling clock signals in accordance with an instruction in said instruction memory means, wherein each of said pairs of first and second sampling clock signals is out of phase with the other pairs of first and second sampling clock signals, and wherein said selected one of said plurality of analog-to-digital converter circuits converts a first analog signal into said first digital signal in accordance with the first sampling clock signal of a selected one of said pairs of first and second sampling clock signals, and said selected one of said plurality of digital-to-analog converter circuits converts said second digital signal into a second analog signal in accordance with the second sampling clock signal of said selected one of said pairs of first and second sampling clock signals.

Claim 33

A digital signal processor according to claim 27, wherein said digital signal processor is formed on a single semiconductor substrate.

Claim 34

A digital signal processor according to claim 27, further comprising a host processor interfaced with said processing unit.

Claim 35

A digital signal processor comprising: a plurality of first external input terminals; a plurality of second external input terminals; a plurality of first external output terminals; a plurality of second external output terminals; first selector means coupled to said plurality of second external input terminals and for selecting one of said plurality of second external input terminals in accordance with a first selection signal; a plurality of analog-to-digital converter circuits, wherein one of said plurality of analog-to-digital converter circuits is coupled to said first selector means, and the remaining plurality of analog-to-digital converters is coupled to said plurality of first external input terminals so that each of the remaining plurality of analog-to-digital converter circuits corresponds to a predetermined one of said first external input terminals; second selector means for selecting one of said plurality of analog-to-digital converter circuits in accordance with a second selection signal; third selector means coupled to said plurality of second external output terminals and for selecting one of said plurality of second external output terminals in accordance with a third selection signal; a plurality of digital-to-analog converter circuits, wherein one of said plurality of digital-to-analog converter circuits is couple to said third selector means and wherein the remaining plurality of digital-to-analog converter circuits is coupled to said plurality of first external output terminals so that each of the remaining plurality of analog-to-digital converter circuits corresponds to a predetermined one of said first external output terminals; fourth selector means for selecting one of said plurality of digital-to-analog converter circuits in accordance with a fourth selection signal; and a processing unit coupled to said second and fourth selector means, wherein said processing unit inputs a first digital signal from said selected one of said plurality of analog-to-digital converter circuits and outputs a second digital signal to said selected one of said plurality of digital-to-analog converter circuits, and said processing unit including, instruction memory means for storing instructions to execute corresponding predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said second selection signal for indicating selection of said one of said plurality of analog-to-digital converter circuits and include said fourth selection signal for indicating selection of one of said plurality of digital-to-analog converter circuits, arithmetic logic means for performing addition and subtraction operations in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting first and second sampling clock signals in response to a value set in accordance with an instruction in said instruction memory means, wherein said selected one of said plurality of analog-to-digital converter circuits converts a first analog signal into said first digital signal in accordance with said first sampling clock signal, and wherein said selected one of said plurality of digital to analog convert circuits converts said second digital signal into a second analog signal in accordance with said second sampling clock signal.

Claim 36

A digital signal processor comprising: a plurality of first external input terminals; a plurality of second external input terminals; a plurality of first external output terminals; a plurality of second external output terminals; first selector means coupled to said plurality of second external input terminals and for selecting one of said plurality of second external input terminals in accordance with a first selection signal; a plurality of analog-to-digital converter circuits, wherein one of said plurality of analog-to-digital converter circuits is coupled to said first selector means, and the remaining plurality of analog-to-digital converters is coupled to said plurality of first external input terminals so that each of the remaining plurality of analog-to-digital converter circuits corresponds to a predetermined one of said first external input terminals; second selector means for selecting one of said plurality of analog-to-digital converter circuits in accordance with a second selection signal; third selector means coupled to said plurality of second external output terminals and for selecting one of said plurality of second external output terminals in accordance with a third selection signal; a plurality of digital-to-analog converter circuits, wherein one of said plurality of digital-to-analog converter circuits is couple to said third selector means and wherein the remaining plurality of digital-to-analog converter circuits is coupled to said plurality of first external output terminals so that each of the remaining plurality of analog-to-digital converter circuits corresponds to a predetermined one of said first external output terminals; fourth selector means for selecting one of said plurality of digital-to-analog converter circuits in accordance with a fourth selection signal; and a processing unit coupled to said second and fourth selector means, wherein said processing unit inputs a first digital signal from said selected one of said plurality of analog-to-digital converter circuits and outputs a second digital signal to said selected one of said plurality of digital-to-analog converter circuits, and said processing unit including, instruction memory means for storing instructions to execute corresponding predetermined operations, instruction decode means for outputting control signals in accordance with an instruction provided from said instruction memory means, wherein said control signals include said second selection signal for indicating selection of said one of said plurality of analog-to-digital converter circuits and include said fourth selection signal for indicating selection of one of said plurality of digital-to-analog converter circuits, arithmetic logic means for performing addition and subtraction operations in accordance with said control signals, multiply means for performing a multiply operation in accordance with said control signals, and timer means for outputting first and second sampling clock signals in response to a value set in accordance with an instruction in said instruction memory means, wherein said selected one of said plurality of analog-to-digital converter circuits converts a first analog signal into said first digital signal in accordance with said first sampling clock signal, and wherein said selected one of said plurality of digital to analog convert circuits converts said second digital signal into a second analog signal in accordance with said second sampling clock signal.

Claim 37

A digital signal processor according to claim 30, wherein said first and second sampling clock signals are out of phase with each other.

Claim 38

A digital signal processor according to claim 30, wherein said digital signal processor is formed on a single semiconductor substrate.

Claim 39

A digital signal processor according to claim 30, wherein said first, second, third and fourth selection signals are two-bit control signals.

Claim 40

A digital signal processor according to claim 30, further comprising a host processor interfaced with said processing unit.