US5227665A
Expired / Lapsed
US
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Semiconductor integrated circuit device
Assignee: Sharp Corp
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Filing: 1991-12-27
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Granted: 1993-07-13
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Expires: 2011-12-27
Abstract
Abstract There is provided a semiconductor integrated circuit device in which a unit circuit element row is formed by connecting unit circuit elements in a second direction, whose first length in a first direction crossing the second direction is predetermined and second length in the second direction can be varied, and a plurality of unit circuit element rows are connected to each other by connecting lines. The semiconductor integrated circuit device includes a first unit circuit element arranged apart from the nearest connecting line along the first direction by a first reference distance and a second unit circuit element projected in the first direction and arranged apart from the nearest connecting line by a second reference distance which is shorter than the first reference distance, whose second length in the second direction is reduced in comparison with the first length of the first unit circuit element.
Inventors
- 👤 Youichi Nakamura
- 👤 Yoshiki Shibata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:02
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; Y; Y10; Y10S; Y10S257/00; Y10S257/909
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
156 words
A semiconductor integrated circuit including a plurality of unit circuit element rows connected to each other by connecting lines, each of said plurality of unit circuit element rows having a first predetermined length in a first direction crossing a second direction and having a second variable length in said second direction and a plurality of unit circuit element rows being formed by connecting unit circuit elements in said second direction, said semiconductor integrated circuit device comprising: a first unit circuit element arranged apart from the nearest connecting line along the first direction by a first reference distance; and a second unit circuit element having a third length in said first direction and arranged apart from said nearest connecting line by a second reference distance which is shorter than said first reference distance and having a fourth length in said second direction which is reduced as compared with said second length of said first unit circuit element.
Claim 2
Dependent Claim
156 words
A semiconductor integrated circuit including a plurality of unit circuit element rows connected to each other by connecting lines, each of said plurality of unit circuit element rows having a first predetermined length in a first direction crossing a second direction and having a second variable length in said second direction and a plurality of unit circuit element rows being formed by connecting unit circuit elements in said second direction, said semiconductor integrated circuit device comprising: a first unit circuit element arranged apart from the nearest connecting line along the first direction by a first reference distance; and a second unit circuit element having a third length in said first direction and arranged apart from said nearest connecting line by a second reference distance which is shorter than said first reference distance and having a fourth length in said second direction which is reduced as compared with said second length of said first unit circuit element.
Claim 3
Dependent Claim
53 words
A semiconductor integrated circuit device as set forth in claim 1, wherein said second reference distance corresponds to a distance between said nearest connecting line along said first direction and said second unit circuit element which prevents signal interference between said nearest connecting line and said second unit circuit element from being generated.
Claim 4
Dependent Claim
27 words
A semiconductor integrated circuit device as set forth in claim 1, wherein said first and second unit circuit elements comprise standard cells each having predetermined logic functions.
Claim 5
Dependent Claim
20 words
A semiconductor integrated circuit device as set forth in claim 3, wherein said standard cell is an inverter logic cell.
Claim 6
Independent Claim
151 words
A method of forming a semiconductor integrated circuit device comprising the steps of: (a) connecting a plurality of unit circuit elements to each other by connecting lines; (b) forming each of said plurality of unit circuit elements to have a first predetermined length in a first direction crossing a second direction and a second variable length in said second direction wherein unit circuit elements are connected in said second direction; (c) arranging a first unit circuit element apart from the nearest connecting line along said first direction by a first reference distance; and (d) arranging a second unit circuit element having a third length in said first direction apart from said nearest connecting line by a second reference distance which is shorter than said first reference distance and having a fourth length in said second direction which is reduced as compared with said second length of said first unit circuit elements.
Claim 7
Independent Claim
151 words
A method of forming a semiconductor integrated circuit device comprising the steps of: (a) connecting a plurality of unit circuit elements to each other by connecting lines; (b) forming each of said plurality of unit circuit elements to have a first predetermined length in a first direction crossing a second direction and a second variable length in said second direction wherein unit circuit elements are connected in said second direction; (c) arranging a first unit circuit element apart from the nearest connecting line along said first direction by a first reference distance; and (d) arranging a second unit circuit element having a third length in said first direction apart from said nearest connecting line by a second reference distance which is shorter than said first reference distance and having a fourth length in said second direction which is reduced as compared with said second length of said first unit circuit elements.
Claim 8
Dependent Claim
52 words
A method of forming a semiconductor integrated circuit device as set forth in claim 5, wherein said second reference distance separates said nearest connecting line and said second unit circuit element by a distance which prevents signal interference between said nearest connecting line and said second unit circuit element from being generated.
References Cited (Backward Citations)
JPS6329949A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-12 | 1997-01-11 | 1997-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-12 | 2001-01-11 | 2001-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-12 | 2005-01-11 | 2005-07-13 | $7700.00 | Window Closed / Lapsed |