At-speed testing of core logic

Claim 1

Method of testing an integrated circuit device having inputs, an input combinational logic stage, outputs, an output combinational logic stage, a core sequential logic stage connected by pipeline stages between the input and output stages and a clock input to the pipeline stages, comprising: providing a stream of clock pulses of period "t"; generating a first stream of clock bursts including a sequence of three first new clock pulses of period "t" followed by a first dead cycle having a duration of at least "t"; generating a second stream of clock bursts including a sequence of three second new clock pulses of period "t" followed by a second dead cycle having a duration of at least "t"; generating a third stream of clock bursts including a sequence of three third new clock pulses of period "t" followed by a third dead cycle having a duration of at least "t"; offsetting the first, second and third streams of clock bursts, to ensure that there is a dead cycle following every clock pulse; providing a first strobe during the first dead cycles, at a time at least "t" after the last of each three of the first new clock pulses in the bursts of three first new clock pulses; providing a second strobe during the second dead cycles, at a time at least "t" after the last of each three of the second new clock pulses in the bursts of three second new clock pulses; providing a third strobe during the third dead cycles, at a time at least "t" after the last of each three of the third new clock pulses in the bursts of three third new clock pulses; in a first pass, applying the first stream of clock bursts to the clock input of the pipeline stages, while applying test patterns to the inputs of the device; in a second pass, applying the second stream of clock bursts to the clock input of the pipeline stages, while applying the same test patterns to the inputs of the device; in a third pass, applying the stream of clock bursts to the clock input of the pipeline stages, while applying the same test patterns to the inputs of the device; in the first pass, strobing, with the first strobe, the outputs of the device, and reading the resultant states of the outputs; in the second pass, strobing, with the second strobe, the outputs of the device, and reading the resultant states of the outputs; and in the third pass, strobing, with the third stroke, the outputs of the device, and reading the resultant states of the outputs.