US5225721A
Expired / Lapsed
US
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Signal translator for interconnecting CMOS and BiCMOS logic gates
Assignee: Unisys Corp
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Filing: 1991-12-18
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Granted: 1993-07-06
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Expires: 2011-12-18
Abstract
Abstract A signal translator circuit receives digital input signals of one voltage polarity and translates them to digital output signals of an opposite polarity. One embodiment of the translator converts conventional CMOS signal levels of +5 and 0 volts to modified CMOS signal levels of 0 and -5.2 volts. Another embodiment of the translator converts the 0 and -5.2 volt signals to the +5 and 0 volt signals. Both embodiments of the translator are made of transistors whose breakdown voltage only slightly exceeds +5 volts.
Inventors
- 👤 Laszlo V. Gal
- 👤 Craig T. Prunty
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/018528
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
124 words
A signal translator circuit, which receives digital input signals of one voltage polarity and produces a digital output signals with an opposite polarity, comprising: a first resistance means coupled to a positive voltage bus and a second resistance means coupled to a negative voltage bus; a P-channel transistor having a source and drain coupled in series between said first and second resistance means and having a gate coupled to a ground bus; an N-channel transistor having a gate coupled to an input terminal for receiving said input signal, and having a source and drain coupled respectively to said gate and source of said P-channel transistor; and, an output terminal coupled to said drain of said P-channel transistor on which said output signal is generated.
Claim 2
Dependent Claim
124 words
A signal translator circuit, which receives digital input signals of one voltage polarity and produces a digital output signals with an opposite polarity, comprising: a first resistance means coupled to a positive voltage bus and a second resistance means coupled to a negative voltage bus; a P-channel transistor having a source and drain coupled in series between said first and second resistance means and having a gate coupled to a ground bus; an N-channel transistor having a gate coupled to an input terminal for receiving said input signal, and having a source and drain coupled respectively to said gate and source of said P-channel transistor; and, an output terminal coupled to said drain of said P-channel transistor on which said output signal is generated.
Claim 3
Dependent Claim
60 words
A circuit according to claim 1 wherein said first resistive device has a resistance R 1 , said N-channel transistor has an ON drain-source resistance R N , said P-channel transistor has a threshold voltage V TP , said positive voltage bus carries a voltage V + , and: V + R N /(R N +R 1 )<|V TP |.
Claim 4
Dependent Claim
60 words
A circuit according to claim 2 wherein said second resistive device has a resistance R 2 , said P-channel transistor has an ON source-drain resistance R P , said negative voltage bus carries a voltage V - , and: (V + +V - ) (R P )/(R 1 +R 2 +R P )<(larger of V + and V - ).
Claim 5
Dependent Claim
35 words
A circuit according to claim 3 wherein: (larger of V + and V - )>(V + +V - )R/ 2 /(R 1 +R 2 +R P )>0.8 (larger of V + and V - ).
Claim 6
Dependent Claim
22 words
A circuit according to claim 4 wherein: R 1 >R N , R 2 >R P , R 2 >R 1 .
Claim 7
Dependent Claim
16 words
A circuit according to claim 5 wherein: R 1 /R N is between 1.5 and 10.
Claim 8
Dependent Claim
15 words
A circuit to claim 5 wherein: R 2 /R P is between 2 and 10.
Claim 9
Dependent Claim
16 words
A circuit according to claim 5 wherein: R 2 /R 1 is between 3 and 10.
Claim 10
Dependent Claim
60 words
A circuit according to claim 1 wherein said second resistive device has a resistance R 2 , said P-channel transistor has an ON drain-source resistance R P , said N-channel transistor has a threshold voltage V TN , said negative voltage bus carries a voltage V - , and V - R P /(R P +R 2 )<|V TN |.
Claim 11
Dependent Claim
59 words
A circuit according to claim 9 wherein said first resistive device has a resistance R 1 , said N-channel transistor has an ON source-drain resistance R N , said positive voltage bus carries a voltage V + , and: (V + +V - )R N /(R 1 +R 2 +R N )<(larger of V + and V - ).
Claim 12
Dependent Claim
24 words
A circuit according to claim 10 wherein: O<V + -(V + +V - )R 2 /(R 1 +R 2 +R N )<0.2V + .
Claim 13
Dependent Claim
22 words
A circuit according to claim 11 wherein: R 2 >R P , R 1 >R N , R 1 >R 2 .
Claim 14
Dependent Claim
16 words
A circuit according to claim 11 wherein: R 2 /R P is between 1.5 and 10.
Claim 15
Dependent Claim
15 words
A circuit to claim 11 wherein: R 1 /R N is between 2 and 10.
Claim 16
Dependent Claim
16 words
A circuit according to claim 11 wherein: R 1 /R 2 is between 3 and 10.
Claim 17
Dependent Claim
124 words
A signal translator circuit, which receives digital input signals of one voltage polarity and produces a digital output signals with an opposite polarity, comprising: a first resistance means coupled to a positive voltage bus and a second resistance means coupled to a negative voltage bus; an N-channel transistor having a source and drain coupled in series between said first and second resistance means and having a gate coupled to a ground bus; a P-channel transistor having a gate coupled to an input terminal for receiving said input signal, and having a source and drain coupled respectively to said gate and source of said N-channel transistor; and, an output terminal coupled to said drain of said N-channel transistor on which said output signal is generated.
Claim 18
Dependent Claim
124 words
A signal translator circuit, which receives digital input signals of one voltage polarity and produces a digital output signals with an opposite polarity, comprising: a first resistance means coupled to a positive voltage bus and a second resistance means coupled to a negative voltage bus; an N-channel transistor having a source and drain coupled in series between said first and second resistance means and having a gate coupled to a ground bus; a P-channel transistor having a gate coupled to an input terminal for receiving said input signal, and having a source and drain coupled respectively to said gate and source of said N-channel transistor; and, an output terminal coupled to said drain of said N-channel transistor on which said output signal is generated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-05 | 1997-01-04 | 1997-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-05 | 2001-01-04 | 2001-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-05 | 2005-01-04 | 2005-07-06 | $7700.00 | Window Closed / Lapsed |