Redundant random access memory device equipped with encoder coupled between programming circuits and redundant word line driving circuits

Claim 1

A semiconductor memory device fabricated on a single semiconductor chip, comprising: a) a plurality of memory cell array blocks each implemented by a plurality of memory cells arranged in rows and columns, memory cells in first rows selected from said rows serving as regular memory cells, memory cells in second rows selected from said rows serving as redundant memory cells; b) a plurality of regular word line groups respectively associated with said plurality of memory cell array blocks, and each having a plurality of regular word lines respectively associated with said first rows for selectively allowing data bits to be read out from said regular memory cells; c) a plurality of word line driving circuits respectively associated with said plurality of regular word line groups, and selectively driving said plurality of word lines of said associated word line groups; d) a plurality of redundant word line groups respectively associated with said plurality of memory cell array blocks, and each having a plurality of redundant word lines respectively associated with said second rows for selectively allowing data bits to be read out from said redundant memory cells, said plurality of redundant word lines of each redundant word line group being respectively replaceable with defective regular word lines which are selected from said plurality of regular word lines of said associated memory cell array block and which are coupled with defective regular memory cells; e) a plurality of redundant word line driving circuit groups respectively associated with said plurality of memory cell array blocks, and each having a plurality of redundant word line driving circuits coupled with said redundant word lines of the associated redundant word line group for selectively allowing data bits from said redundant memory cells; f) a plurality of programming circuits respectively associated with said plurality of memory cell array blocks, and each storing row addresses respectively assigned to said defective regular word lines of the associated memory cell array block, if any, each of said plurality of programming circuits monitoring internal row address bits to see whether or not one of said defective word lines is designated, each of said plurality of programming circuits being operative to produce a multi-bit enable signal indicative of one of said defective word lines indicated by said internal row address bits and a prohibiting signal for canceling enabled state of said word line driving circuit when said internal address bits are indicative of said address assigned to one of said defective word lines; and g) an encoder unit supplied with said multi-bit enable and prohibiting signals from said programming circuits, and operative to produce a coded signal supplied to said plurality of word line driving circuits as well as to said plurality of redundant word line driving circuit groups.