Sequence generator

Claim 2

An improved sequence generator for use with a source of successive bits of random data, said improved sequence generator comprising: shift register means for storing said bits of data, said shift register means having a feedback loop; switch means for selecting between said source means, in a first mode of operation, and said feedback loop, in a second mode of operation, for input to said shift register means; and control logic means for switching said switch means from said second mode to said first mode as said source means provides a each successive bit of random data.

Claim 3

The invention of claim 1 wherein said feedback loop includes first function means for providing a function of the data bits stored in said shift register means.

Claim 4

The invention of claim 2 including second function means for providing a function of the output of said source means and the output of said first function means.

Claim 5

The invention of claim 3 wherein said switch means switches between the output of said first function means in said second mode to the output of said second function means in said first mode.

Claim 6

The invention of claim 1 wherein said shift register means includes a shift register consisting essentially of cascaded flip-flop circuits.

Claim 7

An improved sequence generator for use with an encryption system comprising: source means for providing successive bits of random data; shift register means for storing said bits of data, said shift register means having a feedback loop, said shift register means including a shift register consisting essentially of cascaded flip-flop circuits; switch means for selecting between said source means, in a first mode of operation, and said feedback loop, in a second mode of operation, for input to said shift register means; first function means disposed in said feedback loop for providing a function of the data bits stored in said shift register; second function means for providing a function of the output of said source means and the output of said first function means; and control logic means for switching said switch means from said second mode to said first mode as said source means provides a each successive bit of random data, said control logic means switching switch means between the output of said first function means in said second mode to the output of said second function means in said first mode.

Claim 8

An improved sequence generator for use with an encryption system comprising: source means for providing successive bits of random data; shift register means for storing said bits of data, said shift register means having a feedback loop, said shift register means including a shift register consisting essentially of cascaded flip-flop circuits; switch means for selecting between said source means, in a first mode of operation, and said feedback loop, in a second mode of operation, for input to said shift register means; first function means disposed in said feedback loop for providing a function of the data bits stored in said shift register; second function means for providing a function of the output of said source means and the output of said first function means; and control logic means for switching said switch means from said second mode to said first mode as said source means provides a each successive bit of random data, said control logic means switching switch means between the output of said first function means in said second mode to the output of said second function means in said first mode.

Claim 9

An improved method of randomizing an encryption circuit including the steps of: providing successive bits of random data; storing the bits of random data in a shift register having a feedback loop; selecting either the bits of random data, in a first mode of operation, or the feedback loop, in a second mode of operation, for input to the shift register; and selecting the first mode of operation as each successive bit of random data is provided and otherwise operating in said second mode.

Claim 10

An improved method of randomizing an encryption circuit including the steps of: providing successive bits of random data; storing the bits of random data in a shift register having a feedback loop; selecting either the bits of random data, in a first mode of operation, or the feedback loop, in a second mode of operation, for input to the shift register; and selecting the first mode of operation as each successive bit of random data is provided and otherwise operating in said second mode.

Claim 11

The invention of claim 7 wherein said step of selecting said feedback loop includes selecting a function of the data bits stored in said shift register for input to the shift register.

Claim 12

The invention of claim 8 wherein said step of selecting the bits of random data includes selecting a function of the successive bits of random data and the output of said first function for input to the shift register.

Claim 13

A sequence generator for use with a source of successive bits of random data, said sequence generator comprising: a shift register for storing said bits of random data, said shift register having a feedback loop; a switch for selecting between said random data source in a first mode of operation, and said feedback loop, in a second mode of operation, for input to said shift register; control logic for switching said switch between said second mode and said first mode; and an output port for providing a sequence of bits from the contents of said shift register.

Claim 14

A sequence generator for use with a source of successive bits of random data, said sequence generator comprising: a shift register for storing said bits of random data, said shift register having a feedback loop; a switch for selecting between said random data source in a first mode of operation, and said feedback loop, in a second mode of operation, for input to said shift register; control logic for switching said switch between said second mode and said first mode; and an output port for providing a sequence of bits from the contents of said shift register.

Claim 15

The invention of claim 10 wherein said feedback loop includes a first function generator for providing a first function of the data bits stored in said shift register for input to said shift register.

Claim 16

The invention of claim 11 wherein said first function generator includes a logic gate and said first function includes a logic function.

Claim 17

The invention of claim 12 wherein said logic gate includes an Exclusive or (XOR) gate and said logic function includes an Exclusive or (XOR) function.

Claim 18

The invention of claim 11 including a second function generator for providing a second function of the output of said random data source together with the output of said first function generator for input to said shift register.

Claim 19

The invention of claim 14 wherein said second function generator includes a logic gate and said second function includes a logic function.

Claim 20

The invention of claim 14 wherein said switch switches between the output of said first function generator in said second mode to the output of said second function generator in said first mode.

Claim 21

The invention of claim 10 wherein said control logic switches said switch from said second mode to said first mode as each successive bit is provided from said random data source.

Claim 22

The invention of claim 17 wherein said control logic maintains said switch normally switched to said second mode.

Claim 23

The invention of claim 10 wherein said output port provides bits at a faster rate than said random data source.

Claim 24

The invention of claim 14 wherein said output port provides the bits provided by said second function generator for input to said shift register.

Claim 25

The invention of claim 10 including a clock circuit for providing a timing signal to said random data source and to said output port and a counter for dividing said timing signal provided to said output port as compared to said timing signal provided to said random data source.

Claim 28

The invention of claim 22 wherein said step of selecting said feedback loop includes applying a first function to the data bits stored in said shift register before input to said shift register.

Claim 29

The invention of claim 23 wherein said step of applying a first function comprises applying a logic function to a combination of the data bits stored in said shift register and at least one of said successive bits of random data.

Claim 30

The invention of claim 22, wherein said step of selecting said bits of random data includes applying a second function to a combination of the successive bits of random data and the output of said step of applying a first function before input to said shift register.

Claim 31

The invention of claim 22 wherein the step of providing a sequence of bits at an output port includes applying a logic function to the bits stored in said shift register before providing the bits at an output port.