US5218622A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System of encoding digital signals intended for transmission and/or storage and a corresponding decoding system
Assignee: US Philips Corp
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Filing: 1990-12-20
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Granted: 1993-06-08
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Expires: 2010-12-20
Abstract
Abstract A system of encoding digital signals comprising a source encoder followed by a transmission channel encoder, which is characterized in that in the case in which the source encoder is a variable-length encoding circuit (10), the channel encoder comprises a series arrangement of a sub-assembly of encoding with selective protection and a sub-assembly of encoding without selective protection. The signals being arranged in information component blocks. The system includes a stage for encoding lengths of blocks for determining along the block an accumulated length of code words supplied by said source encoder and ensuring the encoding of block lengths thus determined, a stage for selective protection of said blocks and a stage for multiplexing the signals supplied by said length encoding and selective protection stages. The corresponding decoding system comprises a transmission channel decoder followed by a source decoder, the channel decoder comprising a series arrangement of a sub-assembly for decoding with non-selective protection and a sub-assembly for decoding with n levels of selective protection.
Inventors
- 👤 Khaled Fazel
- 👤 Jean-Jacques Lhuillier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:23
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/85; H04N19/89; H04N19/895; H04N19/30; H04N19/37; H04N19/50; H04N19/60; H04N19/65
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
127 words
A system for encoding digital signals into output code words, said system comprising: a) a source encoder for variable length encoding the bits of said digital signals so as to form a plurality of blocks, each block having a respective number of bits which varies as a function of the information contained in each block; and b) a channel encoder coupled to said source encoder, comprising in series: i. first protection encoding means for further encoding each bit of each of said blocks as a function of the respective bit's sensitivity to transmission errors so as to form a plurality of first code words; and ii. second protection encoding means for encoding said plurality of said first code words so as to form said output code words.
Claim 2
Independent Claim
127 words
A system for encoding digital signals into output code words, said system comprising: a) a source encoder for variable length encoding the bits of said digital signals so as to form a plurality of blocks, each block having a respective number of bits which varies as a function of the information contained in each block; and b) a channel encoder coupled to said source encoder, comprising in series: i. first protection encoding means for further encoding each bit of each of said blocks as a function of the respective bit's sensitivity to transmission errors so as to form a plurality of first code words; and ii. second protection encoding means for encoding said plurality of said first code words so as to form said output code words.
Claim 3
Dependent Claim
86 words
An encoding system as claimed in claim 1, wherein said first protection encoding means comprises: (a) a block length encoding stage for determining and encoding lengths of each of said blocks so as to form respective block length code words; (b) a protection stage coupled to said block length encoding stage, for selectively protecting said blocks; (c) a multiplexing stage coupled to said block length encoding stage and said protection stage, for multiplexing the outputs supplied by said block length encoding stage and said protection stage.
Claim 4
Dependent Claim
140 words
An encoding system as claimed in claim 2, wherein the block length encoding stage comprises: (a) a bit counting circuit, for counting the number of bits forming each block so as to determine its respective bit length; (b) a first memory coupled to said bit counting circuit, for storing the the bit length of each block; (c) a block counting circuit coupled to said bit counting circuit, for counting blocks from end of a block signals supplied by said source encoder; (d) a decision circuit coupled to said block counting circuit and said first memory, for controlling reading of the first memory as a function of the output of said block counting circuit; and (e) an encoding circuit coupled to said decision circuit, for encoding the bit length of each of said blocks into said respective block length code words.
Claim 5
Dependent Claim
78 words
An encoding system as claimed in claim 3, wherein the protection stage comprises: (a) means for classifying the bits of each block in accordance with their sensitivity to transmission errors; (b) means coupled to said selective encoding means, for selective encoding said bits as a function of said classification so as to form classified code words; and (c) means for reducing the number of bits of said classified code words so as to form said second code words.
Claim 6
Dependent Claim
96 words
An encoding system as claimed in claim 4, wherein the means for classifying the bits in accordance with their sensitivity to transmission errors comprise a second memory arranged for receiving and storing said first code words from the source encoder, and a third memory for assigning an address for each of said first code words stored in said second memory and for supplying said first code words in a sequence which is modified as a function of said addressing; the means for selective encoding comprise a Blokh-Zyablov encoder; and the reducing means comprise bit suppressing means.
Claim 7
Dependent Claim
22 words
An encoding system as claimed in claim 5, wherein the multiplexing stage comprises means for controlling the rate of its output signals.
Claim 8
Dependent Claim
29 words
An encoding system as claimed in claim 2, wherein the protection stage comprises means for classifying the bits of each block in accordance with their sensitivity to transmission errors.
Claim 9
Dependent Claim
92 words
An encoding system as claimed in claim 7, wherein the means for classifying the bits in accordance with their sensitivity to transmission errors comprise a second memory arranged for receiving and storing said first code words, and a third memory for assigning an address for each of said first code words stored in said second memory and for supplying said first code words in a sequence which is modified as a function of said addressing; the means for selective encoding comprise a Blokh-Zyablov encoder; and the reducing means comprise bit suppressing means.
Claim 10
Dependent Claim
24 words
An encoding system as claimed in claim 8, wherein the multiplexing stage comprises means for controlling the rate of output from said multiplexing means.
Claim 11
Dependent Claim
74 words
A system for decoding the output code words of claim 1, said system comprising: a) a channel decoder comprising in series: i. second protection decoding means for decoding said output code words into said first code words and ii. first protection decoding means for further decoding each of said first code words so as to form said blocks; and b) a source decoder coupled to said channel decoder so as to receive said blocks.
Claim 12
Dependent Claim
95 words
A decoding system as claimed in claim 10, wherein said first code words comprise a plurality of block length code words and second code words, and wherein said first protection decoding means comprises: (a) a length decoding stage, arranged for decoding said block length code words; (b) a second decoding stage; (c) a demultiplexing stage having an input coupled to said non-selective protection decoding means so as to receive said first code words, for switching the block length code words to said length decoding stage and said second code words to said second decoding stage.
Claim 13
Dependent Claim
108 words
A decoding system as claimed in claim 11, wherein the second decoding stage comprises: (A) means for demultiplexing said said second code words signals when the length of a block exceeds the encoding capacity; (B) selective decoding means comprising a Blokh-Zyablov decoder having n parallel-arranged selective decoding circuits; (C) inverse reducing means, for adapting the format of the signals to be decoded to the capacity of the said selective decoding means when the length of a block is less than said encoding capacity; (D) means for classifying the decoded digital signals in accordance with their sensitivity to transmission errors; (E) storage means for storing the signals thus classified.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |