Orthogonal transformation arithmetic unit

Claim 2

An orthogonal transformation arithmetic unit for performing a discrete cosine transformation with respect to a digital signal and compressing discrete cosine transformed data by quantizing and Huffman-coding processings thereof, said orthogonal transformation arithmetic unit Huffman-decoding the compressed data and demodulating the Huffman-decoded data to a digital signal by performing inverse quantization and an inverse discrete cosine transformation with respect to the Huffman-decoded data, said orthogonal transformation arithmetic unit comprising: a memory section for storing one line block of image data of brightness and color signals converted to digital signals; and a section for processing the discrete cosine transformation and having a preprocessing circuit for performing adding and substracting operations with respect to the image data read out of said memory section such that some values of discrete cosine transformation coefficients used in the discrete cosine transformation are partially set to zero.

Claim 3

An orthogonal transformation arithmetic unit as claimed in claim 1, wherein the discrete cosine transformation processing section performs the discrete cosine transformation with respect to data obtained by performing the adding and subtracting operations about digitally converted data of the brightness and color signals supplied from the memory section.

Claim 4

An orthogonal transformation arithmetic unit for dividing one image into blocks including a plurality of picture elements, said orthogonal transformation arithmetic unit comprising: an orthogonal transformation circuit for performing orthogonal transformation processing with respect to each of the blocks; and an inverse orthogonal transformation circuit for returning orthogonally transformed data to original image data; said inverse orthogonal transformation circuit having a processing block having a variable size and selecting an inverse orthogonal transformation coefficient corresponding to a designated size of the processing block, said inverse orthogonal transformation circuit performing inverse orthogonal transformation processing with respect to the designated size of the processing block.

Claim 5

An orthogonal transformation arithmetic unit for dividing one image into blocks including a plurality of picture elements, said orthogonal transformation arithmetic unit comprising: an orthogonal transformation circuit for performing orthogonal transformation processing with respect to each of the blocks; and an inverse orthogonal transformation circuit for returning orthogonally transformed data to original image data; said inverse orthogonal transformation circuit having a processing block having a variable size and selecting an inverse orthogonal transformation coefficient corresponding to a designated size of the processing block, said inverse orthogonal transformation circuit performing inverse orthogonal transformation processing with respect to the designated size of the processing block.

Claim 6

An orthogonal transformation arithmetic unit as claimed in claim 3, wherein the inverse orthogonal transformation circuit comprises multipliers for performing a multiplying operation with respect to input data and the inverse orthogonal transformation coefficient corresponding to the designated size of the processing block; a gate circuit for judging validation or invalidation of products of said respective multipliers corresponding to the designated size of the processing block; and an adder for adding the products of said multipliers validated by the gate circuit to each other so as to obtain one data.

Claim 7

An orthogonal transformation arithmetic unit for performing a discrete cosine transformation with respect to a digital signal and compressing discrete cosine transformed data by quantizing and Huffman-coding processings thereof, said orthogonal transformation arithmetic unit Huffman-decoding the compressed data and demodulating the Huffman-decoded data to a digital signal by performing inverse quantization and an inverse discrete cosine transformation with respect to the Huffman-decoded data, said orthogonal transformation arithmetic unit having a discrete cosine transformation/inverse discrete cosine transformation processing section for processing the discrete cosine transformation and the inverse discrete cosine transformation; said discrete cosine transformation/inverse discrete cosine transformation processing section comprising: a coefficient memory section for storing coefficients required to perform the discrete cosine transformation and the inverse discrete cosine transformation and transmitting one of said coefficients selected in accordance with a control signal indicative of the discrete cosine transformation or the inverse discrete cosine transformation; a set of main arithmetic circuits for processing both the discrete cosine transformation and the inverse discrete cosine transformation by said transmitted coefficient and commonly used in both the processings of the discrete cosine transformation and the inverse discrete cosine transformation; and a section for selecting discrete cosine transformed data or inverse discrete cosine transformed data in accordance with said control signal.

Claim 8

An orthogonal transformation arithmetic unit for performing a discrete cosine transformation with respect to a digital signal and compressing discrete cosine transformed data by quantizing and Huffman-coding processings thereof, said orthogonal transformation arithmetic unit Huffman-decoding the compressed data and demodulating the Huffman-decoded data to a digital signal by performing inverse quantization and an inverse discrete cosine transformation with respect to the Huffman-decoded data, said orthogonal transformation arithmetic unit having a discrete cosine transformation/inverse discrete cosine transformation processing section for processing the discrete cosine transformation and the inverse discrete cosine transformation; said discrete cosine transformation/inverse discrete cosine transformation processing section comprising: a coefficient memory section for storing coefficients required to perform the discrete cosine transformation and the inverse discrete cosine transformation and transmitting one of said coefficients selected in accordance with a control signal indicative of the discrete cosine transformation or the inverse discrete cosine transformation; a set of main arithmetic circuits for processing both the discrete cosine transformation and the inverse discrete cosine transformation by said transmitted coefficient and commonly used in both the processings of the discrete cosine transformation and the inverse discrete cosine transformation; and a section for selecting discrete cosine transformed data or inverse discrete cosine transformed data in accordance with said control signal.

Claim 9

An orthogonal transformation arithmetic unit of an adaptive discrete cosine transformation coding system for performing an orthogonal transformation with respect to information of a color still image using a discrete cosine transformation, said orthogonal transformation arithmetic unit comprising: a change-over switch for setting the number of sheets of a photographed image storable to a memory section having a constant memory capacity; a compressibility detecting section for automatically setting a quantizing coefficient used to compress an information amount of the photographed image until a predetermined image information amount in accordance with a signal indicative of the number of sheets of the photographed image transmitted from said change-over switch, said compressibility detecting section calculating a compressibility of the information amount and predicting a quality level of the stored photographed image based on said compressibility; and a display section for visually displaying a signal indicative of said image quality level transmitted from said compressibility detecting section.

Claim 10

An orthogonal transformation arithmetic unit of an adaptive discrete cosine transformation coding system for performing an orthogonal transformation with respect to information of a color still image using a discrete cosine transformation, said orthogonal transformation arithmetic unit comprising: a change-over switch for setting the number of sheets of a photographed image storable to a memory section having a constant memory capacity; a compressibility detecting section for automatically setting a quantizing coefficient used to compress an information amount of the photographed image until a predetermined image information amount in accordance with a signal indicative of the number of sheets of the photographed image transmitted from said change-over switch, said compressibility detecting section calculating a compressibility of the information amount and predicting a quality level of the stored photographed image based on said compressibility; and a display section for visually displaying a signal indicative of said image quality level transmitted from said compressibility detecting section.

Claim 11

An orthogonal transformation arithmetic unit as claimed in claim 6, wherein the compressibility detecting section arbitrarily sets the quantizing coefficient such that information of the number of sheets of the photographed image manually set by the change-over switch is stored to the memory section.

Claim 12

An orthogonal transformation arithmetic unit as claimed in claim 6, wherein the display section can display superiority and inferiority of the image quality.