Digital phase detector arrangements

Claim 2

In combination with a digital phase detector for deriving a digital output signal representing phase differences between two input clock signals supplied to the phase detector, circuit means for reducing jitter in said output signal comprising: means for differentiating said output signal to produce a differentiated signal; low-pass filter means for low-pass filtering said differentiated signal to produce a filtered signal; and means for integrating said filtered signal to produce a further digital output signal from which at least some jitter has been removed by said low-pass filter means.

Claim 3

The combination according to claim 1 wherein said circuit means for reducing jitter further comprises means for differentiating said differentiated signal to produce a control signal for controlling a pass-band of said low-pass filter means.

Claim 4

The combination according to claim 2 wherein said control signal is supplied to said low-pass filter means by way of another low-pass filter means.

Claim 5

The combination according to claim 1, wherein said two input clock signals have respective frequencies and wherein said digital phase detector includes first and second counter means for dividing the frequencies of said two input clock signals in the same ratio and supplying respective output signals therefrom, latch circuit means for latching the output signal of said second counter means to produce said digital output signal, and a phase-locked loop circuit controlled by the output signal of said first counter means and including third counter means supplying an output signal therefrom for strobing said latch circuit means.

Claim 6

The combination according to claim 4 wherein said means for differentiating said output signal comprises latch means which receives said digital output signal and is strobed by the output signal of said third counter means, and a modulo subtractor receiving said digital output signal and an output signal from said latch means for producing said differentiated signal.

Claim 7

The combination according to claim 4 wherein said means for integrating comprises latch means, which is strobed by the output signal of said third counter means, and a modulo adder receiving said filtered signal and an output signal from said latch means for producing said further digital output signal.

Claim 8

The combination according to claim 4 wherein said circuit means for reducing jitter further comprises means for differentiating said differentiated signal to produce a control signal for controlling a pass-band of said low-pass filter means.

Claim 9

The combination according to claim 7 wherein said means for differentiating said differentiated signal comprises latch means, which receives said differentiated signal and is strobed by the output signal of said third counter means and a modulo subtractor receiving said differentiated signal and an output signal from said latch means for producing said control signal.

Claim 10

The combination according to claim 7 wherein said control signal is supplied to said low-pass filter means by way of another low-pass filter means.

Claim 11

A digital signal interpolator apparatus for interpolating an input digital signal having a first sample rate so as to derive a sample-rate converted output digital signal having a second sample rate different from said first sample rate, said digital signal interpolator apparatus comprising: a cascaded series of multi-tap interpolation filter means, each of said interpolation filter means having a plurality of selectively employed tap sets; digital phase detector means receiving first and second clock signals having frequencies corresponding to said first and second sample rates and including means for providing a control signal representing phase differences between said first and second clock signals; circuit means for reducing jitter in said control signal including means for differentiating said control signal to produce a differentiated signal, low-pass filter means for low-pass filtering said differentiated signal to produce a filtered signal, and means for integrating said filtered signal to produce a smoothed control signal from which at least some jitter has been removed; means for supplying said smoothed control signal to each of said interpolation filter means for selecting one of said tap sets to be employed in the respective interpolation filter means; means to supply said input digital signal to a first of said interpolation filter means of said series; and means to derive said sample-rate converted output digital signal from a last of said interpolation filter means of said series.

Claim 12

A digital signal interpolator apparatus for interpolating an input digital signal having a first sample rate so as to derive a sample-rate converted output digital signal having a second sample rate different from said first sample rate, said digital signal interpolator apparatus comprising: a cascaded series of multi-tap interpolation filter means, each of said interpolation filter means having a plurality of selectively employed tap sets; digital phase detector means receiving first and second clock signals having frequencies corresponding to said first and second sample rates and including means for providing a control signal representing phase differences between said first and second clock signals; circuit means for reducing jitter in said control signal including means for differentiating said control signal to produce a differentiated signal, low-pass filter means for low-pass filtering said differentiated signal to produce a filtered signal, and means for integrating said filtered signal to produce a smoothed control signal from which at least some jitter has been removed; means for supplying said smoothed control signal to each of said interpolation filter means for selecting one of said tap sets to be employed in the respective interpolation filter means; means to supply said input digital signal to a first of said interpolation filter means of said series; and means to derive said sample-rate converted output digital signal from a last of said interpolation filter means of said series.

Claim 13

The digital signal interpolator apparatus according to claim 10, further comprising random access memory means for storing said tap sets.

Claim 14

The digital signal interpolator apparatus according to claim 10 wherein each said interpolation filter means includes random access memory means for storing the respective selectively employed tap sets and wherein each said interpolation filter means is formed as an integrated circuit.

Claim 15

The digital signal interpolation apparatus according to claim 10, further comprising full resolution digital connections between each said interpolation filter means in said series and the next said interpolation filter means in said series.

Claim 16

The digital signal interpolation apparatus according to claim 10 wherein each said interpolation filter means includes a 16-tap digital filter having 64 of said selectively employed tap sets.

Claim 17

The digital signal interpolation apparatus according to claim 14 wherein said cascaded series of interpolation filter means comprises two said interpolation filter means.