US5214609A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1991-08-29
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Granted: 1993-05-25
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Expires: 2011-08-29
Abstract
Abstract In the semiconductor integrated circuit, the data delay circuit and data latch circuit are connected between the sense amplifier circuit and the output buffer circuit. A pulse signal for controlling the output buffer is first generated according to a pulse output signal of the address change detection circuit, and then a latch signal which permits output data of the data detection circuit obtained before the change of the address input signal to be latched by the data latch circuit for a preset period of time is generated. Next, a delay signal is generated which sets the delay time of the data delay circuit to be short in a case where data detected by the data detection circuit is not output from the output buffer circuit, and sets the delay time of the data delay circuit to be long in a case where data is output from the output buffer circuit. Generation of the delay signal is interrupted after the pulse signal of the address change detection circuit is interrupted. As a result, the power source variation at the time of output data change or erroneous operation due to noise input from the exterior can be prevented. Further, the driving ability of the output buffer transistor can be set to a large value so that a highly reliable semiconductor integrated circuit in which the operation margin of the integrated circuit with respect to the power source variation and noise can be made large while keeping the data readout speed high can be obtained.
Inventors
- 👤 Hiroto Nakai
- 👤 Hiroshi Iwahashi
- 👤 Nobuaki Hiraga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:01
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/02; G11C16/00; G11C7/06; G11C7/062; G11C7/10; G11C7/1006; G11C7/1051; G11C7/1057; G11C7/106; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
312 words
A semiconductor integrated circuit comprising: address change detection circuit for detecting change of an address input and generating a pulse signal; memory cells for storing data; a data detection circuit controlled by an external input signal for controlling the operation of the semiconductor integrated circuit, for detecting data stored in the memory cell; at least two delay circuits having different delay time characteristics, connected to the output terminal of said data detection circuit, and controlled according to the pulse signal of said address change detection circuit; a logic circuit connected to the output terminals of said respective delay circuits and controlled according to the pulse signal from said address change detection circuit, for keeping an output level thereof unchanged when the output data items of said delay circuits are not equal to each other and change the output level when the output data items of said delay circuits become equal to each other in a case where said delay circuits are set in the operative state; a bypass circuit connected between input terminals of said respective delay circuits and the output terminal of said logic circuit, controlled according to the pulse signal of said address change detection circuit and having a delay time characteristic shorter than the delay time characteristics of said respective delay circuits; a latch circuit connected to the output terminal of said logic circuit, the latching operation thereof being controlled according to the pulse signal of said address change detection circuit; an output buffer circuit connected to the output terminal of said latch circuit, for outputting data stored in said memory cell; and an output buffer control circuit for setting up a state in which output data from said data detection circuit is prevented from being output from said output buffer circuit for a preset period of time according to the pulse signal of said address change detection circuit.
Claim 2
Dependent Claim
312 words
A semiconductor integrated circuit comprising: address change detection circuit for detecting change of an address input and generating a pulse signal; memory cells for storing data; a data detection circuit controlled by an external input signal for controlling the operation of the semiconductor integrated circuit, for detecting data stored in the memory cell; at least two delay circuits having different delay time characteristics, connected to the output terminal of said data detection circuit, and controlled according to the pulse signal of said address change detection circuit; a logic circuit connected to the output terminals of said respective delay circuits and controlled according to the pulse signal from said address change detection circuit, for keeping an output level thereof unchanged when the output data items of said delay circuits are not equal to each other and change the output level when the output data items of said delay circuits become equal to each other in a case where said delay circuits are set in the operative state; a bypass circuit connected between input terminals of said respective delay circuits and the output terminal of said logic circuit, controlled according to the pulse signal of said address change detection circuit and having a delay time characteristic shorter than the delay time characteristics of said respective delay circuits; a latch circuit connected to the output terminal of said logic circuit, the latching operation thereof being controlled according to the pulse signal of said address change detection circuit; an output buffer circuit connected to the output terminal of said latch circuit, for outputting data stored in said memory cell; and an output buffer control circuit for setting up a state in which output data from said data detection circuit is prevented from being output from said output buffer circuit for a preset period of time according to the pulse signal of said address change detection circuit.
Claim 3
Dependent Claim
284 words
A semiconductor integrated circuit comprising: a 3-input logic circuit for keeping an output thereof unchanged when the logic levels of two delayed signal inputs are not equal to each other and changing the output when the logic levels of the two delayed signal inputs become equal to each other; an inverter connected to the output terminal of said 3-input logic circuit, an output thereof being input as one of the inputs of said 3-input logic circuit; and a transfer gate connected at one end to the output terminal of said inverter and controlled according to a preset control signal; wherein said 3-input logic circuit includes first to third transistors of P-channel type series-connected between a first power source potential node and an output node, fourth and fifth transistors of P-channel type series-connected between said first power source potential node and said output node, a serial connection node between said fourth and fifth transistors being connected to a serial connection node between said second and third transistors, six and seventh transistors of N-channel type series-connected between a second power source potential node and said output node, eighth and ninth transistors of N-channel type series-connected between said second power source potential node and said output node, and tenth and eleventh transistors of N-channel type series-connected between said second power source potential node and said output node, the gates of said second, third, sixth and eighth transistors being supplied with one of the two delayed signal inputs, the gates of said first, fifth, seventh and tenth transistors being supplied with the other of the two delayed signal inputs, and the gates of said fourth, ninth and eleventh transistors being supplied with an output signal of said inverter.
Claim 4
Dependent Claim
284 words
A semiconductor integrated circuit comprising: a 3-input logic circuit for keeping an output thereof unchanged when the logic levels of two delayed signal inputs are not equal to each other and changing the output when the logic levels of the two delayed signal inputs become equal to each other; an inverter connected to the output terminal of said 3-input logic circuit, an output thereof being input as one of the inputs of said 3-input logic circuit; and a transfer gate connected at one end to the output terminal of said inverter and controlled according to a preset control signal; wherein said 3-input logic circuit includes first to third transistors of P-channel type series-connected between a first power source potential node and an output node, fourth and fifth transistors of P-channel type series-connected between said first power source potential node and said output node, a serial connection node between said fourth and fifth transistors being connected to a serial connection node between said second and third transistors, six and seventh transistors of N-channel type series-connected between a second power source potential node and said output node, eighth and ninth transistors of N-channel type series-connected between said second power source potential node and said output node, and tenth and eleventh transistors of N-channel type series-connected between said second power source potential node and said output node, the gates of said second, third, sixth and eighth transistors being supplied with one of the two delayed signal inputs, the gates of said first, fifth, seventh and tenth transistors being supplied with the other of the two delayed signal inputs, and the gates of said fourth, ninth and eleventh transistors being supplied with an output signal of said inverter.
Claim 5
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 1, wherein said delay circuit and said bypass circuit are controlled according to the pulse signal of said address change detection circuit.
References Cited (Backward Citations)
US5086414A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-24 | 1996-11-23 | 1997-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-24 | 2000-11-23 | 2001-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-24 | 2004-11-23 | 2005-05-25 | $7700.00 | Window Closed / Lapsed |