Electrostatic discharge protective circuit of shunting transistors

Claim 1

An electrostatic discharge protective apparatus for an electronic circuit on an integrated circuit substrate comprising in combination: a plurality of input/output pads arranged in proximity to one another, a conductor arranged in proximity to each input/output pad of said plurality of input/output pads and electrically connected to a further bonding pad, a first plurality of semiconductor devices operatively connected respectively between adjacent input/output pads of said plurality of input/output pads and said bonding pad, each semiconductor device of said first plurality of semiconductor devices is normally on, a second plurality of semiconductor devices operatively connected respectively to each input/output pad of said plurality of input/output pads and to said conductor, and, each semiconductor device of said second plurality of semiconductor devices is normally on, and means for generating delayed bias and delivering said bias to the controlling terminals of said first and second plurality of semiconductor devices, upon receipt of power to said electronic circuit; said delayed bias means turns off said first and second pluralities of semiconductor devices.