Dimmable fluorescent lamp ballast

Claim 2

A combination comprising: a source providing ordinary AC power line voltage at a pair of power line terminals; rectifier circuit connected with the power line terminals and operable to provide a DC voltage at a pair of DC terminals; the absolute magnitude of the DC voltage being substantially higher than the peak absolute magnitude of the AC power line voltage; a gas discharge lamp having a pair of lamp terminals; and inverter circuit connected between the DC terminals and the lamp terminals; the inverter circuit being operable to supply an alternating lamp voltage across the lamp terminals, thereby to cause an alternating lamp current of substantially constant amplitude to flow through the lamp.

Claim 3

The combination of claim 1 wherein, at least at certain times, a conductive path exists between one of the DC terminals and one of the power line terminals.

Claim 4

The combination of claim 1 wherein the inverter circuit includes an L-C tank circuit resonant at or near the frequency of the lamp voltage.

Claim 5

The combination of claim 1 wherein the inverter circuit has an adjustment input operable, in response to receiving an adjustment action, to adjust the magnitude of the lamp current by way of adjusting the frequency of the alternating lamp voltage.

Claim 6

The combination of claim 4 wherein the adjustment input is electrically isolated from the power line terminals.

Claim 7

The combination of claim 1 wherein the inverter circuit is characterized by including two transistors series-connected across the DC terminals.

Claim 8

The combination of claim 1 wherein: (i) the inverter circuit includes a transistor having an emitter, a base, and a collector; (ii) current flows between the emitter and the collector once for a brief period during each complete cycle of the alternating lamp voltage; and (iii) the duration of the brief period is shorter than half the duration of each such complete cycle.

Claim 9

The combination of claim 1 wherein: (i) the inverter circuit includes a transistor having a pair of control input terminals; (ii) a control voltage is provided to the control input terminals for a brief period during each complete cycle of the alternating lamp voltage, thereby to render the transistor conductive; and (iii) the duration of the brief period is distinctly shorter than half the duration of each such complete cycle.

Claim 10

The combination of claim 1 wherein: (i) the inverter circuit includes a transistor having a pair of control input terminals; (ii) a control voltage is provided to the control input terminals, thereby to render the transistor conductive for a brief period during each complete cycle of the alternating lamp voltage; and (iii) the duration of the brief period is distinctly shorter than half the duration of each such complete cycle.

Claim 11

The combination of claim 1 wherein: (i) the inverter circuit includes a transistor having a pair of control input terminals; (ii) a control voltage is provided to the control input terminals, thereby to render the transistor conductive for a brief period during each complete cycle of the alternating lamp voltage; (iii) the duration of the brief period is shorter than half the duration of each such complete cycle; and (iv) the peak-to-peak magnitude of the control voltage is substantially larger than twice the forward voltage drop of an ordinary semiconductor diode.

Claim 12

The combination of claim 1 wherein the inverter circuit is characterized by having two terminals across which exists a periodic AC voltage having a fundamental period consisting of four distinct time regions: (i) a first time region during which the instantaneous magnitude of the periodic AC voltage remains at a substantially constant negative level; (ii) a second time region during which the instantaneous magnitude of the periodic AC voltage increases at a substantially constant rate; (iii) a third time region during which the instantaneous magnitude of the periodic AC voltage remains at a substantially constant positive level; and (iv) a fourth time region during which the instantaneous magnitude of the periodic AC voltage decreases at a substantially constant rate; the duration of the fourth time region being about equal to or longer than one tenth of the duration of the third time region.

Claim 13

The combination of claim 1 wherein the inverter circuit is characterized by including: (i) two alternately conducting transistors; and (ii) for each transistor, a saturable inductor means.

Claim 14

The combination of claim 1 wherein the inverter circuit is characterized by including: (i) two alternately conducting transistors; and (ii) for each transistor, a saturable current transformer.

Claim 15

The combination of claim 1 wherein the magnitude of the DC voltage is about equal to twice the peak magnitude of the power line voltage.

Claim 16

The combination of claim 1 wherein the rectifier circuit, the gas discharge lamp, and the inverter circuit are all mounted on a base operable to be inserted into and held by an ordinary Edison-type lamp socket.

Claim 17

A combination comprising: a source providing ordinary AC power line voltage at a pair of power line terminals; rectifier circuit connected with the power line terminals and operable to provide a DC voltage at a pair of DC terminals; a gas discharge lamp having a pair of lamp terminals; and an inverter connected in circuit between the DC terminals and the lamp terminals; the inverter being operable to supply an alternating inverter output voltage at a pair of inverter output terminals; the inverter output terminals being connected with the lamp terminals by way of current-limiting circuitry, thereby to cause an alternating lamp current to flow through the lamp; the inverter being characterized by including a transistor having a pair of terminals across which exists a transistor voltage and through which a transistor current periodically flows; the absolute magnitude of the transistor voltage varying periodically between a substantially constant minimum level and a substantially constant maximum level; the maximum level having a duration approximately equal to that of the minimum level; the magnitude of the maximum level being substantially higher than that of the minimum level; the transistor current flowing only during periods when the absolute magnitude of the transistor voltage is at or below the minimum level.

Claim 18

A combination comprising: a source providing ordinary AC power line voltage at a pair of power line terminals; rectifier circuit connected with the power line terminals and operable to provide a DC voltage at a pair of DC terminals; a gas discharge lamp having a pair of lamp terminals; and an inverter connected in circuit between the DC terminals and the lamp terminals; the inverter being operable to supply an alternating inverter output voltage at a pair of inverter output terminals; the inverter output terminals being connected with the lamp terminals by way of current-limiting circuitry, thereby to cause an alternating lamp current to flow through the lamp; the inverter being characterized by including a transistor having a pair of terminals across which exists a transistor voltage and through which a transistor current periodically flows; the absolute magnitude of the transistor voltage varying periodically between a substantially constant minimum level and a substantially constant maximum level; the maximum level having a duration approximately equal to that of the minimum level; the magnitude of the maximum level being substantially higher than that of the minimum level; the transistor current flowing only during periods when the absolute magnitude of the transistor voltage is at or below the minimum level.

Claim 19

The combination of claim 16 wherein the transistor has a pair of control terminals across which exists a control voltage varying periodically between a minimum voltage level and a maximum voltage level; the absolute magnitude of the difference between the maximum voltage level and the minimum voltage level being substantially larger than twice the absolute magnitude of the forward voltage drop of an ordinary semiconductor diode.

Claim 20

The combination of claim 16 wherein, during each complete period of the alternating inverter output voltage, the absolute magnitude of the transistor voltage remains at or below the minimum level for a total duration that is substantially shorter than half the duration of the complete period.

Claim 21

A combination comprising: a source providing ordinary AC power line voltage at a pair of power line terminals; rectifier circuit connected with the power line terminals and operable to provide a DC voltage at a pair of DC terminals; a gas discharge lamp having a pair of lamp terminals; and inverter circuit connected between the DC terminals and the lamp terminals; the inverter circuit being operable to supply an alternating lamp voltage across the lamp terminals, thereby to cause a lamp current to flow through the lamp; the inverter circuit being characterized by including a first transistor having a first pair of control terminals across which exists a periodically varying control voltage; the magnitude of the control voltage varying by an amount that is substantially larger than twice the absolute magnitude of the forward voltage drop of an ordinary semiconductor diode.

Claim 22

A combination comprising: a source providing ordinary AC power line voltage at a pair of power line terminals; rectifier circuit connected with the power line terminals and operable to provide a DC voltage at a pair of DC terminals; a gas discharge lamp having a pair of lamp terminals; and inverter circuit connected between the DC terminals and the lamp terminals; the inverter circuit being operable to supply an alternating lamp voltage across the lamp terminals, thereby to cause a lamp current to flow through the lamp; the inverter circuit being characterized by including a first transistor having a first pair of control terminals across which exists a periodically varying control voltage; the magnitude of the control voltage varying by an amount that is substantially larger than twice the absolute magnitude of the forward voltage drop of an ordinary semiconductor diode.

Claim 23

The combination of claim 19 wherein the periodically varying control voltage is characterized by being of non-sinusoidal waveform.

Claim 24

The combination of claim 19 wherein the first transistor is series-connected with a second transistor to form a series-combination; the series-combination being connected across the DC terminals.