Improper writing prevention circuit and a memory device and a data processing device which include the circuit

Claim 2

An improper writing prevention circuit for use with a device having means for supplying a source voltage and memory means adapted to receive the source voltage, the source voltage having a value, the memory means including a state selection terminal ,the circuit comprising: source voltage detection means for detecting the value of the source voltage and for generating a first control signal having a value which is dependant on the value of th source voltage; receiving means for receiving predetermined data; storage means, including a test register, for receiving reference data and for storing the received reference data; validity check means, operably connected to said receiving means and to said storage means, for performing a writing test which determines whether or not the reference data is consistent with the predetermined data and for generating a second control signal having a value which is dependent on the determination; and state selection means for receiving said first and second control signals from said source voltage detection means and said validity check means, respectively, and for producing a state selection signal to be applied to the state selection terminal oft the memory means in accordance with the values of said first and second control signals.

Claim 3

An improper writing prevention circuit according to claim 1, wherein said the improper writing prevention circuit is formed as a monolithic semiconductor integrated circuit.

Claim 4

A memory device, comprising: memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the states; source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dependent on the value of the source voltage; storage means, including a test register, for receiving and storing reference data and for receiving and storing predetermined data, the reference data being stored in said test register; a data bus operably connected to said memory means and said storage means; validity check means, operably connected to said storage means, for performing a writing test which determines whether or not the reference data is consistent with the predetermined data, and for generating a second control signal having a value which is dependent on the determination; and state selection means for receiving said first an second control signals from said source voltage detection means and said validity check means, respectively, and for producing a state selection signal to be applied to said state selection terminal in accordance with the values of said first and second control signals.

Claim 5

A memory device, comprising: memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the states; source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dependent on the value of the source voltage; storage means, including a test register, for receiving and storing reference data and for receiving and storing predetermined data, the reference data being stored in said test register; a data bus operably connected to said memory means and said storage means; validity check means, operably connected to said storage means, for performing a writing test which determines whether or not the reference data is consistent with the predetermined data, and for generating a second control signal having a value which is dependent on the determination; and state selection means for receiving said first an second control signals from said source voltage detection means and said validity check means, respectively, and for producing a state selection signal to be applied to said state selection terminal in accordance with the values of said first and second control signals.

Claim 6

A memory device as define in claim 3, wherein said the memory means is formed as a monolithic semiconductor integrated circuit.

Claim 7

A memory device according to claim 4, wherein said the monolithic semiconductor integrated circuit and at least one of said source voltage detection means, said storage means, said data bus, said validity check means and said state selection means are in the form of an IC card.

Claim 8

A memory device according to claim 3 formed as a monolithic semiconductor integrated circuit.

Claim 9

A memory device according to claim 6, wherein said monolithic semiconductor integrated circuit is in the form of an IC card.

Claim 10

A memory device according to claim 3, wherein said test register defines a first test register, the device further comprising: a second test register adapted to receive and store data from said data bus, wherein said validity check means inverts data read out from said second test register and determines whether the inverted data is consistent with the predetermined data.

Claim 11

A memory device as defined in claim 8, wherein said memory means is formed as a monolithic semiconductor integrated circuit.

Claim 12

A memory device according to claim 9, wherein said monolithic semiconductor integrated circuit at least one of said source voltage detection means, said storage means, said data bus, said validity check means and said stat selection means are in the form of an IC card.

Claim 13

A memory device according to claim 8 formed as a monolithic semiconductor integrated circuit.

Claim 14

A memory device according to claim 11, wherein said monolithic semiconductor integrated circuit is in the form of an IC card.

Claim 15

A memory device, comprising: memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the sates; a data bu adapted to supply data to said memory means; source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dependent on the value of the source voltage; and an improper writing prevention circuit including a read and write test register adapted to receive data from said data bus, and state selection signal generating means for receiving said first control signal and data from said test register, for analyzing the data from said test register, and for generating a state selection signal to be applied to said sate selection terminal in a accordance with the value of said first control signal.

Claim 16

A memory device, comprising: memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the sates; a data bu adapted to supply data to said memory means; source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dependent on the value of the source voltage; and an improper writing prevention circuit including a read and write test register adapted to receive data from said data bus, and state selection signal generating means for receiving said first control signal and data from said test register, for analyzing the data from said test register, and for generating a state selection signal to be applied to said sate selection terminal in a accordance with the value of said first control signal.

Claim 17

A memory device as defined in claim 13, wherein said memory means is formed as a monolithic semiconductor integrated circuit.

Claim 18

A memory device according to claim 14, wherein said monolithic semiconductor integrated circuit and at least one of said source voltage detection means, said data bus, and said improper writing prevention circuit are in the form of an IC card.

Claim 19

A memory device according to claim 13 formed as a monolithic semiconductor integrated circuit.

Claim 20

A memory device according to claim 16, wherein said monolithic semiconductor integrated circuit is in the form of an IC card.

Claim 21

A memory device as defined in claim 13, wherein said state selection signal generating means comprises a decoder adapted to decode the data stored in said test register and to produce a second control signal having a value which is dependent on the decoding, and sate selection control means for generating the state selection signal in accordance with the values of said first and second control signals.

Claim 22

A memory device as defined in claim 18, wherein said memory means is formed as a monolithic semiconductor integrated circuit.

Claim 23

A memory device as defined in claim 19, wherein said monolithic semiconductor integrated circuit and at least one of said source voltage detection means, said data bus, and said improper writing detection circuit are in the form of an IC card.

Claim 24

A memory device according to claim 18 formed as a monolithic semiconductor integrated circuit.

Claim 25

A memory device according to claim 21, wherein said monolithic semiconductor integrated circuit is in he form of an IC card.

Claim 26

A data processing device, comprising: memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the sates; source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dependent on the value of the source voltage; storage means, including a test register, for receiving and storing reference data and for receiving and storing predetermined data, the reference data being stored in said test register; a data bus operably connected to said memory means and said storage means; validity check means, operably connected to said storage means, for performing a writing test which determines whether or not the reference data is consistent with the predetermined data, and for generating a second control signal having a value which is dependent on the determination; state selection means for receiving said first an second control signals from said source voltage detection means and said validity check means, respectively, and for producing a state selection signal to be applied to said state selection terminal in accordance with the values of said first and second control signals; and a control block including microprocessor means for writing reference data into said first test register prior to an actual writing operation.

Claim 27

A data processing device, comprising: memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the sates; source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dependent on the value of the source voltage; storage means, including a test register, for receiving and storing reference data and for receiving and storing predetermined data, the reference data being stored in said test register; a data bus operably connected to said memory means and said storage means; validity check means, operably connected to said storage means, for performing a writing test which determines whether or not the reference data is consistent with the predetermined data, and for generating a second control signal having a value which is dependent on the determination; state selection means for receiving said first an second control signals from said source voltage detection means and said validity check means, respectively, and for producing a state selection signal to be applied to said state selection terminal in accordance with the values of said first and second control signals; and a control block including microprocessor means for writing reference data into said first test register prior to an actual writing operation.

Claim 28

A data processing device, comprising: memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the sates; a data bus adapted to supply data to said memory means; source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dep3ndent on the value of the source voltage; an improper writing prevention circuit including a read and write test register adapted to receive data from said data bus, a decoder adapted to decode the data stored in said test register and to produce a second control signal having a value which is dependent on the decoding, and state selection control means for generating the state selection signal to be applied to said state selection terminal in accordance with the values of said first and second control signals; and a control block including microprocessor means for writing predetermined data into said read and write test register prior to an actual writing operation.

Claim 29

A data processing device, comprising: memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the sates; a data bus adapted to supply data to said memory means; source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dep3ndent on the value of the source voltage; an improper writing prevention circuit including a read and write test register adapted to receive data from said data bus, a decoder adapted to decode the data stored in said test register and to produce a second control signal having a value which is dependent on the decoding, and state selection control means for generating the state selection signal to be applied to said state selection terminal in accordance with the values of said first and second control signals; and a control block including microprocessor means for writing predetermined data into said read and write test register prior to an actual writing operation.