US5212685A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control circuit for half-duplex/simplex interface in communication system
Assignee: International Business Machines Corp
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Filing: 1991-03-21
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Granted: 1993-05-18
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Expires: 2011-03-21
Abstract
Abstract An interface circuit for connecting an electrical half-duplex system to an optical simplex system includes logic which permits keep-alive signals to be gated onto the transmitting simplex fiber when data is not being received on the half-duplex conductor. The interface circuit includes receive logic connected in parallel with the receive data path. The receive logic responds to predetermined bit patterns in the received data to control the receive and transmit data path connections. The interface circuit also includes transmit logic connected in parallel with the transmit data path. The transmit logic responds to bit patterns in the data on the transmit data path to selectively gate the output of a keep-alive oscillator onto the transmit simplex fiber.
Inventors
- 👤 George R. Stilwell, Jr.
- 👤 Theodore B. Vojnovich
- 👤 Robert L. Walker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:25
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/14; H04L5/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
303 words
A half-duplex/simplex control circuit for providing an interface between a half-duplex line and a pair of simplex lines, one of said simplex lines being used to transmit data selectively forwarded from the half-duplex line and the other of said simplex lines being used to receive data to be selectively forwarded to the half-duplex line, said control circuit comprising: a receive control logic circuit connected in parallel with the receiving simplex line and the half-duplex line, said receive control logic circuit being responsive to received simplex data to generate a first receive control signal upon detection of a first pattern in such data and a second receive control signal upon detection of a second or a third pattern in such data; first gating means responsive to the first receive control signal to enable forwarding of received simplex data to the half-duplex line while inhibiting forwarding of received half-duplex data to the transmitting simplex line, said first gating means also being responsive to the second receive control signal to inhibit forwarding of received simplex data while enabling forwarding of received half-duplex data; a keep alive signal source for providing a continuous idle signal which may be selectively forwarded to the transmitting simplex line; a transmit control logic circuit connected in parallel with the half-duplex line and the transmitting simplex line, said transmit control logic circuit being responsive to data received on the half-duplex line to generate a first transmit control signal upon detection of a fourth pattern in such data; and second gating means responsive to the first transmit control signal to enable forwarding of received half-duplex data to the transmitting simplex line, said second gating means also being responsive to the second transmit control signal to inhibit forwarding of received half-duplex data while connecting the keep alive signal source to the transmitting simplex line.
Claim 2
Dependent Claim
303 words
A half-duplex/simplex control circuit for providing an interface between a half-duplex line and a pair of simplex lines, one of said simplex lines being used to transmit data selectively forwarded from the half-duplex line and the other of said simplex lines being used to receive data to be selectively forwarded to the half-duplex line, said control circuit comprising: a receive control logic circuit connected in parallel with the receiving simplex line and the half-duplex line, said receive control logic circuit being responsive to received simplex data to generate a first receive control signal upon detection of a first pattern in such data and a second receive control signal upon detection of a second or a third pattern in such data; first gating means responsive to the first receive control signal to enable forwarding of received simplex data to the half-duplex line while inhibiting forwarding of received half-duplex data to the transmitting simplex line, said first gating means also being responsive to the second receive control signal to inhibit forwarding of received simplex data while enabling forwarding of received half-duplex data; a keep alive signal source for providing a continuous idle signal which may be selectively forwarded to the transmitting simplex line; a transmit control logic circuit connected in parallel with the half-duplex line and the transmitting simplex line, said transmit control logic circuit being responsive to data received on the half-duplex line to generate a first transmit control signal upon detection of a fourth pattern in such data; and second gating means responsive to the first transmit control signal to enable forwarding of received half-duplex data to the transmitting simplex line, said second gating means also being responsive to the second transmit control signal to inhibit forwarding of received half-duplex data while connecting the keep alive signal source to the transmitting simplex line.
Claim 3
Dependent Claim
186 words
A half-duplex/simplex control circuit for providing an interface between a half-duplex line and a pair of simplex lines, said control circuit comprising: a first control circuit responsive to a first pattern in data received on a first of the simplex lines to forward such data to the half-duplex line while blocking any connection between the half-duplex line and the second simplex line, said first pattern being a maximum of three bits in length, said first control circuit also being responsive to second and third patterns in such data to block any connection between the half-duplex line and the first simplex line while enabling a connection between the half-duplex line and the second simplex line; and a second control circuit responsive to a fourth pattern in data received on the half-duplex line to enable a connection between the half-duplex line and the second simplex line, said fourth pattern being a maximum of two bits in length, said second control circuit also being responsive to a fifth pattern of data received on the half-duplex line to block any connection between the half-duplex line and the second simplex line.
Claim 4
Dependent Claim
186 words
A half-duplex/simplex control circuit for providing an interface between a half-duplex line and a pair of simplex lines, said control circuit comprising: a first control circuit responsive to a first pattern in data received on a first of the simplex lines to forward such data to the half-duplex line while blocking any connection between the half-duplex line and the second simplex line, said first pattern being a maximum of three bits in length, said first control circuit also being responsive to second and third patterns in such data to block any connection between the half-duplex line and the first simplex line while enabling a connection between the half-duplex line and the second simplex line; and a second control circuit responsive to a fourth pattern in data received on the half-duplex line to enable a connection between the half-duplex line and the second simplex line, said fourth pattern being a maximum of two bits in length, said second control circuit also being responsive to a fifth pattern of data received on the half-duplex line to block any connection between the half-duplex line and the second simplex line.
Claim 5
Dependent Claim
63 words
A half-duplex/simplex control circuit in accordance with claim 2 further including a keep alive signal source for providing a continuous idle signal as an output for being selectively forwarded to the second simplex line and means responsive to detection of the fifth pattern by the second control circuit to gate the output of said keep alive signal source to the second simplex line.
Claim 6
Dependent Claim
69 words
A half-duplex/simplex control circuit in accordance with claim 3 further including a first delay circuit in series with the half-duplex line and the second simplex line for delaying half-duplex data to allow the second control circuit time to respond to the fourth pattern in the half-duplex data by blocking the output of the keep alive signal source before the half-duplex data can be introduced onto the second simplex line.
Claim 7
Dependent Claim
71 words
A half-duplex/simplex control circuit in accordance with claim 4 further including a second delay circuit in series with the half-duplex line and the first simplex line for delaying simplex data to allow the first control circuit time to respond to the first pattern in the simplex data by blocking the connection between the second simplex line and the half-duplex line before the simplex data can be introduced onto the half-duplex line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-17 | 1996-11-16 | 1997-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-17 | 2000-11-16 | 2001-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-17 | 2004-11-16 | 2005-05-18 | $7700.00 | Window Closed / Lapsed |