Power on reset circuit having hysteresis inverters

Claim 2

A circuit, comprising: first means responsive to a first power supply potential from a first power supply conductor for developing a first reset signal having a first logic state when said first power supply potential is less than a first predetermined threshold, said first reset signal having a second logic state when said first power supply potential is greater than a second predetermined threshold; and second means responsive to said first power supply potential for developing a second reset signal having a first logic state when said first power supply potential is less than a third predetermined threshold, said second reset signal having a second logic state when said first power supply potential is greater than a fourth predetermined threshold, said second means receiving said first reset signal to disable said second means until said first power supply potential reaches said second predetermined threshold.

Claim 3

The circuit of claim 1 further including: third means operating in response to an input clock signal for generating first and second clock signals having opposite phase; and a delay circuit having an input coupled for receiving said second reset signal and having first and second control inputs for receiving said first and second clock signals respectively, said delay circuit providing a delayed second reset signal at an output following a predetermined number of cycles of said first and second clock signals.

Claim 4

The circuit of claim 2 wherein said second means includes: a first transistor having a gate, a drain and a source, said drain and gate receiving said first power supply potential; a second transistor having a gate, a drain and a source, said drain and gate being coupled together to said source of said first transistor; a third transistor having a gate, a drain and a source, said drain being coupled to said source of said second transistor; a first inverter circuit with hysteresis having an input coupled to said source of said third transistor at a first node and having an output at a second node; a second inverter having an input coupled to said second node and having an output for providing said second reset signal; and a NOR gate having first and second inputs and an output, said first input receiving said first reset signal, said second input receiving said second reset signal, said output being coupled to said gate of said third transistor.

Claim 5

The circuit of claim 3 wherein said second means further includes: a fourth transistor having a gate, a drain and a source, said drain being coupled to said first node, said gate receiving said first reset signal, said source being coupled to a second power supply conductor; a fifth transistor having a gate, a drain and a source, said source being coupled to said first power supply conductor, said gate being coupled to said second node, said drain being coupled to said first node; a third inverter having an input coupled to said output of said NOR gate and having an output; and a sixth transistor having a gate, a drain and a source, said source being coupled to said first node, said gate being coupled to said output of said third inverter, said drain being coupled to said output of said second inverter.

Claim 6

The circuit of claim 4 wherein said first inverter circuit includes: a seventh transistor having a gate, a drain and a source, said source being coupled to said first power supply conductor, said gate being coupled to said first node; an eighth transistor having a gate, a drain and a source, said source being coupled to said drain of said seventh transistor, said gate being coupled to said first node, said drain being coupled to said second node; a ninth transistor having a gate, a drain and a source, said source being coupled to said source of said eighth transistor, said gate being coupled to said second node, said drain being coupled to said second power supply conductor; a tenth transistor having a gate, a drain and a source, said source being coupled to said second power supply conductor, said gate being coupled to said first node; an eleventh transistor having a gate, a drain and a source, said source being coupled to said drain of said tenth transistor, said gate being coupled to said first node, said drain being coupled to said second node; and a twelfth transistor having a gate, a drain and a source, said source being coupled to said source of said tenth transistor, said gate being coupled to said second node, said drain being coupled to said first power supply conductor.

Claim 7

The circuit of claim 5 wherein said first means includes: a thirteenth transistor having a gate, a drain and a source, said drain and gate receiving said first power supply potential; a fourth inverter circuit with hysteresis having an input coupled to said source of said thirteenth transistor at a third node and having an output for providing said first reset signal at a fourth node; and a capacitor coupled between said third node and said second power supply conductor.

Claim 8

The circuit of claim 6 wherein said fourth inverter circuit includes: a fourteenth transistor having a gate, a drain and a source, said source being coupled to said first power supply conductor, said gate being coupled to said third node; a fifteenth transistor having a gate, a drain and a source, said source being coupled to said drain of said fourteenth transistor, said gate being coupled to said third node, said drain being coupled to said fourth node; a sixteenth transistor having a gate, a drain and a source, said source being coupled to said source of said fifteenth transistor, said gate being coupled to said fourth node, said drain being coupled to said second power supply conductor; a seventeenth transistor having a gate, a drain and a source, said source being coupled to said second power supply conductor, said gate being coupled to said third node; an eighteenth transistor having a gate, a drain and a source, said source being coupled to said drain of said seventeenth transistor, said gate being coupled to said third node, said drain being coupled to said fourth node; and a nineteenth transistor having a gate, a drain and a source, said source being coupled to said drain of said seventeenth transistor, said gate being coupled to said fourth node, said drain being coupled to said first power supply conductor.

Claim 9

The circuit of claim 7 wherein said third means includes: a divider circuit having a clock input, a reset input and an output, said clock input receiving said input clock signal, said reset input receiving said first reset signal; and an opposite phase clock generator circuit having an input coupled to said output of said divider circuit and having first and second output for providing said first and second clock signals having opposite phase.

Claim 10

The circuit of claim 8 wherein said third means further includes: a fifth inverter having an input for receiving said first reset signal and having output; a first AND gate having first and second inputs and an output, said first input being coupled to said output of said fifth inverter, said second input being coupled to said first output of said opposite phase clock generator, said output providing said first clock signal; and a second AND gate having first and second inputs and an output, said first input being coupled to said output of said fifth inverter, said second input being coupled to said second output of said opposite phase clock generator, said output providing said second clock signal.

Claim 11

The circuit of claim 9 wherein said delay circuit includes: a twentieth transistor having a gate, a drain and a source, said drain being coupled to said output of said second inverter, said gate receiving said first clock signal; a sixth inverter having an input coupled to said source of said twentieth transistor and having an output; a twenty-first transistor having a gate, a drain and a source, said drain being coupled to said input of said sixth inverter, said gate receiving said first reset signal, said source being coupled to said second power supply conductor; a twenty-second transistor having a gate, a drain and a source, said drain being coupled to said output of said sixth inverter, said gate receiving said second clock signal; a seventh inverter having an input coupled to said source of said twenty-second transistor and having an output for providing said delayed second reset signal; and a twenty-second transistor having a gate, a drain and a source, said drain being coupled to said input of said seventh inverter, said gate receiving said first reset signal, said source being coupled to said first power supply conductor.

Claim 12

A power-on reset circuit responsive to a first power supply potential from a first power supply conductor and having an output for providing a reset signal after said first power supply potential reaches a threshold, comprising: first means responsive to said first power supply potential for developing a first reset signal having a first logic state when said first power supply potential is less than a first predetermined threshold, said first reset signal having a second logic state when said first power supply potential is greater than a second predetermined threshold; a first transistor having a gate, a drain and a source, said drain and gate receiving said first power supply potential; a second transistor having a gate, a drain and a source, said drain and gate being coupled together to said source of said first transistor; a third transistor having a gate, a drain and a source, said drain being coupled to said source of said second transistor; a first inverter circuit with hysteresis having an input coupled to said source of said third transistor at a first node and having an output at a second node; a second inverter having an input coupled to said second node and having an output; and a NOR gate having first and second input and an output, said first input receiving said first reset signal, said second input receiving said second reset signal, said output being coupled to said gate of said third transistor.

Claim 13

A power-on reset circuit responsive to a first power supply potential from a first power supply conductor and having an output for providing a reset signal after said first power supply potential reaches a threshold, comprising: first means responsive to said first power supply potential for developing a first reset signal having a first logic state when said first power supply potential is less than a first predetermined threshold, said first reset signal having a second logic state when said first power supply potential is greater than a second predetermined threshold; a first transistor having a gate, a drain and a source, said drain and gate receiving said first power supply potential; a second transistor having a gate, a drain and a source, said drain and gate being coupled together to said source of said first transistor; a third transistor having a gate, a drain and a source, said drain being coupled to said source of said second transistor; a first inverter circuit with hysteresis having an input coupled to said source of said third transistor at a first node and having an output at a second node; a second inverter having an input coupled to said second node and having an output; and a NOR gate having first and second input and an output, said first input receiving said first reset signal, said second input receiving said second reset signal, said output being coupled to said gate of said third transistor.

Claim 14

The power-on reset circuit of claim 11 further including: second means operating in response to an input clock signal for generating first and second clock signals having opposite phase; and a delay circuit having an input coupled for receiving said second reset signal and having first and second control inputs for receiving said first and second clock signals, said delay circuit providing a delayed second reset signal at an output following a predetermined number of cycles of said first and second clock signals.

Claim 15

The power-on reset circuit of claim 12 further includes: a fourth transistor having a gate, a drain and a source, said drain being coupled to said first node, said gate receiving said first reset signal, said source being coupled to a second power supply conductor; a fifth transistor having a gate, a drain and a source, said source being coupled to said first power supply conductor, said gate being coupled to said second node, said drain being coupled to said first node; a third inverter having an input coupled to said output of said NOR gate and having an output; and a sixth transistor having a gate, a drain and a source, said source being coupled to said first node, said gate being coupled to said output of said third inverter, said drain being coupled to said output of said second inverter.

Claim 16

The power-on reset circuit of claim 13 wherein said first inverter circuit includes: a seventh transistor having a gate, a drain and a source, said source being coupled to said first power supply conductor, said gate being coupled to said first node; an eighth transistor having a gate, a drain and a source, said source being coupled to said drain of said seventh transistor, said gate being coupled to said first node, said drain being coupled to said second node; a ninth transistor having a gate, a drain and a source, said source being coupled to said source of said eighth transistor, said gate being coupled to said second node, said drain being coupled to said second power supply conductor; a tenth transistor having a gate, a drain and a source, said source being coupled to said second power supply conductor, said gate being coupled to said first node; an eleventh transistor having a gate, a drain and a source, said source being coupled to said drain of said tenth transistor, said gate being coupled to said first node, said drain being coupled to said second node; and a twelfth transistor having a gate, a drain and a source, said source being coupled to said source of said tenth transistor, said gate being coupled to said second node, said drain being coupled to said first power supply conductor.

Claim 17

The power-on reset circuit of claim 14 wherein said first means includes: a thirteenth transistor having a gate, a drain and a source, said drain and gate receiving said first power supply potential; a fourth inverter circuit with hysteresis having an input coupled to said source of said thirteenth transistor at a third node and having an output for providing said first reset signal at a fourth node; and a capacitor coupled between said third node and said second power supply conductor.

Claim 18

The power-on reset circuit of claim 15 wherein said fourth inverter circuit includes: a fourteenth transistor having a gate, a drain and a source, said source being coupled to said first power supply conductor, said gate being coupled to said third node; a fifteenth transistor having a gate, a drain and a source, said source being coupled to said drain of said fourteenth transistor, said gate being coupled to said third node, said drain being coupled to said fourth node; a sixteenth transistor having a gate, a drain and a source, said source being coupled to said source of said fifteenth transistor, said gate being coupled to said fourth node, said drain being coupled to said second power supply conductor; a seventeenth transistor having a gate, a drain and a source, said source being coupled to said second power supply conductor, said gate being coupled to said third node; an eighteenth transistor having a gate, a drain and a source, said source being coupled to said drain of said seventeenth transistor, said gate being coupled to said third node, said drain being coupled to said fourth node; and a nineteenth transistor having a gate, a drain and a source, said source being coupled to said drain of said seventeenth transistor, said gate being coupled to said fourth node, said drain being coupled to said first power supply conductor.

Claim 19

The power-on reset circuit of claim 16 wherein said second means includes: a divider circuit having a clock input, a reset input and an output, said clock input receiving said input clock signal, said reset input receiving said first reset signal; and an opposite phase clock generator circuit having an input coupled to said output of said divider circuit and having first and second output for providing said first and second clock signals having opposite phase.

Claim 20

The power-on reset circuit of claim 17 wherein said second means further includes: a fifth inverter having an input for receiving said first reset signal and having output; a first AND gate having first and second inputs and an output, said first input being coupled to said output of said fifth inverter, said second input being coupled to said first output of said opposite phase clock generator, said output providing said first clock signal; and a second AND gate having first and second inputs and an output, said first input being coupled to said output of said fifth inverter, said second input being coupled to said second output of said opposite phase clock generator, said output providing said second clock signal.

Claim 21

The power-on reset circuit of claim 18 wherein said delay circuit includes: a twentieth transistor having a gate, a drain and a source, said drain being coupled to said output of said second inverter, said gate receiving said first clock signal; a sixth inverter having an input coupled to said source of said twentieth transistor and having an output; a twenty-first transistor having a gate, a drain and a source, said drain being coupled to said input of said sixth inverter, said gate receiving said first reset signal, said source being coupled to said second power supply conductor; a twenty-second transistor having a gate, a drain and a source, said drain being coupled to said output of said sixth inverter, said gate receiving said second clock signal; a seventh inverter having an input coupled to said source of said twenty-second transistor and having an output for providing said delayed second reset signal; and a twenty-second transistor having a gate, a drain and a source, said drain being coupled to said input of said seventh inverter, said gate receiving said first reset signal, said source being coupled to said first power supply conductor.

Claim 22

A power on reset circuit, comprising: first means responsive to a first power supply potential for developing a first reset signal when said first power supply potential is greater than a first predetermined threshold; second means responsive to said first power supply potential for developing a second reset signal when said first power supply potential is greater than a second predetermined threshold, said second means receiving said first reset signal to disable said second means until said first power supply potential reaches said first predetermined threshold; third means operating in response to an input clock signal for generating first and second clock signals having opposite phase; and a delay circuit having an input coupled for receiving said second reset signal and having first and second control inputs for receiving said first and second clock signals, said delay circuit providing a delayed second reset signal at an output following a predetermined number of cycles of said first and second clock signals.

Claim 23

A power on reset circuit, comprising: first means responsive to a first power supply potential for developing a first reset signal when said first power supply potential is greater than a first predetermined threshold; second means responsive to said first power supply potential for developing a second reset signal when said first power supply potential is greater than a second predetermined threshold, said second means receiving said first reset signal to disable said second means until said first power supply potential reaches said first predetermined threshold; third means operating in response to an input clock signal for generating first and second clock signals having opposite phase; and a delay circuit having an input coupled for receiving said second reset signal and having first and second control inputs for receiving said first and second clock signals, said delay circuit providing a delayed second reset signal at an output following a predetermined number of cycles of said first and second clock signals.