Data processing system having apparatus for increasing the execution speed of bit field instructions

Claim 2

A data processing system comprising: execution means for executing instructions, said instructions including an instruction for causing said execution means to perform a bit processing operation on a field which contains two or more words within a memory and an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word of said memory, each instruction including operation codes for indicating whether said each instruction is an instruction for causing said execution means to perform a bit processing operation on a field which contains two or more words or an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word; and said execution means including means for calculating a bit width of each field to be processed to determined the number of bits in said each field; wherein said execution means, when executing an instruction, determines based on operation codes included in said instruction, whether said instruction is an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word and wherein if said instruction is an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word, a calculation of a bit width by said means for calculating is not performed.

Claim 3

A data processing system according to claim 1, wherein said system is a microprocessor for use with an external memory formed on a single semiconductor chip.

Claim 4

The data processing system as set forth in claim 1, wherein said field of said instruction for causing said execution means to perform a bit processing operation on a field contained within one word is designated by operands of a base address indicating an address as a reference, an offset value indicating a number of bits from the base address to a starting end of said field, and a field width indicating a number of bits in the field, said operands being included within said instruction for causing said execution means to perform a bit processing operation on a field contained within one word.

Claim 5

A data processing system according to claim 3, wherein said system is a microprocessor for use with an external memory formed on a single semiconductor chip.

Claim 6

The processing system as set forth in claim 3, wherein said instruction for causing said execution means to perform a bit processing operation on a field contained within one word is supplied with an offset value as an immediate value by said execution means in response to an operand of said instruction.

Claim 7

A data processing system according to claim 5, wherein said system is a microprocessor for use with an external memory formed on a single semiconductor chip.

Claim 8

The data processing system as set forth in claim 5, wherein said instruction for causing said execution means to perform a bit processing operation on a field contained within one word is supplied with a field width as an immediate value by said execution means in response to an operand of said instruction.

Claim 9

A data processing system according to claim 7, wherein said system is a microprocessor for use with an external memory formed on a single semiconductor chip.

Claim 12

A method according to claim 9, wherein said microprocessor is formed on a single semiconductor chip.

Claim 13

A method as set forth in claim 9, further comprising a step of: aligning data of a field fetched from the memory thereby permitting bit operations to be performed.

Claim 14

A method according to claim 11, wherein said microprocessor is formed on a single semiconductor chip.

Claim 15

A method as set forth in claim 11, wherein said step for processing a field contained within one word includes the step of determining, based on operation codes included in an instruction currently being executed whether a bit width of the field is equal to one word indicating that the instruction currently being executed by said executing unit is an instruction for causing said execution means to perform a bit processing operation on a field contained within one word.

Claim 16

A method according to claim 13, wherein said microprocessor is formed on a single semiconductor chip.

Claim 17

A microprocessor comprising: execution means for executing instructions, said instructions including and instruction for causing said execution means to perform a bit processing operation on a field which contains two or more words within a memory and an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word of said memory, each instruction includes operation codes for indicating whether said each instruction is an instruction for causing said execution means to perform a bit processing operation on a field which contains two or more words or an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word; and said execution means including means for calculating a bit width of each field to be processed to determine the number of bits in said each field; wherein said execution means, when executing an instruction, determines based on operation codes included in said instruction, whether said instruction is an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word and if said instruction is an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word, a calculation of a bit width of said field by said means for calculating is not performed; wherein said field of said instruction for causing said execution means to perform a bit processing operation on a field contained within one word is designated by operands of a base address indicating an address as a reference, an offset value indicating a number of bits from the base address to a starting end of said field and a field width indicating a number of bits within the field, said operands being included in said instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word; and wherein said instruction for causing said execution means to perform a bit processing operation on a field contained within one word is supplied with an offset value and a field width as immediate values by said execution means in response to operands of said instruction.

Claim 18

A microprocessor comprising: execution means for executing instructions, said instructions including and instruction for causing said execution means to perform a bit processing operation on a field which contains two or more words within a memory and an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word of said memory, each instruction includes operation codes for indicating whether said each instruction is an instruction for causing said execution means to perform a bit processing operation on a field which contains two or more words or an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word; and said execution means including means for calculating a bit width of each field to be processed to determine the number of bits in said each field; wherein said execution means, when executing an instruction, determines based on operation codes included in said instruction, whether said instruction is an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word and if said instruction is an instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word, a calculation of a bit width of said field by said means for calculating is not performed; wherein said field of said instruction for causing said execution means to perform a bit processing operation on a field contained within one word is designated by operands of a base address indicating an address as a reference, an offset value indicating a number of bits from the base address to a starting end of said field and a field width indicating a number of bits within the field, said operands being included in said instruction for causing said execution means to perform a bit processing operation on a field which is contained within one word; and wherein said instruction for causing said execution means to perform a bit processing operation on a field contained within one word is supplied with an offset value and a field width as immediate values by said execution means in response to operands of said instruction.

Claim 19

A microprocessor according to claim 15, wherein said microprocessor is formed on a single semiconductor chip.

Claim 20

The microprocessor as set forth in claim 15 wherein said instruction for causing said execution means to perform a bit processing operation on a field which contains two or more words is provided with an operand assignment portion for obtaining an offset value by register indirect processing.

Claim 21

A microprocessor according to claim 17, wherein said microprocessor is formed on a single semiconductor chip.

Claim 22

The microprocessor as set forth in claim 15 wherein said instruction for causing said execution means to perform a bit processing operation on a field which contains two or more words is provided with an operand assignment portion for obtaining a field width by register direct addressing.

Claim 23

A microprocessor according to claim 19, wherein said microprocessor is formed on a single semiconductor chip.