Patent US1853098A successfully refreshed from Google Patents.
US5208564A
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US
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Electronic phase shifting circuit for use in a phased radar antenna array
Assignee: Raytheon Co
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Filing: 1991-12-19
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Granted: 1993-05-04
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Expires: 2011-12-19
Abstract
Abstract A phase shifting circuit (10) which is especially suitable for use as a 180° phase bit for an antenna element in a phased radar antenna array includes a first transmission line (16) connected between first and second diodes (22,24), which are connected to input and output terminals (12,14) respectively. Second and third transmission lines (18,20) are connected in series with each other between the input and output terminals (12,14). A third diode (26) is connected between the junction (28) of the second and third transmission lines (18,20) and ground. The first transmission line (16) is less than one-quarter wavelength long at the operating frequency of the circuit (10), whereas the second and third transmission lines (18,20) are each approximately three-eighths wavelength long. Forward biasing the diodes (22,24,26) causes substantially all of the signal to propagate from the input terminal (12) to the output terminal (14) through the first transmission line (16), producing minimum phase shift. Reverse biasing the diodes (22,24,26) causes a major portion of the signal to propagate through the second and third transmission lines (18,20), producing maximum phase shift.
Inventors
- 👤 Richard W. Burns
- 👤 Darren E. Atkinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:18
CPC Classifications
H; H01; H01P; H01P1/00; H01P1/18; H01P1/185
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
308 words
A phase bit circuit for receiving an input signal and producing an output signal which is selectively shifted in phase by a first predetermined amount or a second predetermined amount relative to the input signal, comprising; input terminal means for inputting the input signal; output terminal means for outputting the output signal; first transmission line means coupled between the input and output terminal means; a first diode coupled between the first transmission line means and the input terminal means; a second diode coupled between the first transmission line means and the output terminal means; second and third transmission line means connected in series with each other between the input and output terminal means, the second and third transmission line means defining a junction therebetween; a third diode coupled between said junction of the second and third transmission line means and ground; and biasing means coupled to the first, second and third diodes for selectively forward biasing the first, second and third diodes to cause substantially all of the input signal to propagate from the input terminal means through the first transmission line means to the output terminal means to constitute the output signal which is shifted in phase relative to the input signal by the first predetermined amount; or reverse biasing the first, second and third diodes to cause a first portion of the input signal to propagate from the input terminal means through the first transmission line means to the output terminal means and a second portion of the input signal to propagate from the input terminal means through the second and third transmission line means to the output terminal means, said first and second portions of the input signal combining at the output terminal means to constitute the output signal which is phase shifted in phase relative to the input signal by the second predetermined amount.
Claim 2
Dependent Claim
308 words
A phase bit circuit for receiving an input signal and producing an output signal which is selectively shifted in phase by a first predetermined amount or a second predetermined amount relative to the input signal, comprising; input terminal means for inputting the input signal; output terminal means for outputting the output signal; first transmission line means coupled between the input and output terminal means; a first diode coupled between the first transmission line means and the input terminal means; a second diode coupled between the first transmission line means and the output terminal means; second and third transmission line means connected in series with each other between the input and output terminal means, the second and third transmission line means defining a junction therebetween; a third diode coupled between said junction of the second and third transmission line means and ground; and biasing means coupled to the first, second and third diodes for selectively forward biasing the first, second and third diodes to cause substantially all of the input signal to propagate from the input terminal means through the first transmission line means to the output terminal means to constitute the output signal which is shifted in phase relative to the input signal by the first predetermined amount; or reverse biasing the first, second and third diodes to cause a first portion of the input signal to propagate from the input terminal means through the first transmission line means to the output terminal means and a second portion of the input signal to propagate from the input terminal means through the second and third transmission line means to the output terminal means, said first and second portions of the input signal combining at the output terminal means to constitute the output signal which is phase shifted in phase relative to the input signal by the second predetermined amount.
Claim 3
Dependent Claim
56 words
A circuit as in claim 1, in which the first, second and third transmission line means have first, second and third lengths respectively, the sum of the second and third lengths being larger than the first length such that the second predetermined amount of phase shift is larger than the first predetermined amount of phase shift.
Claim 4
Dependent Claim
37 words
A circuit as in claim 2, in which the first, second and third lengths are selected such that the second predetermined amount of phase shift is approximately 180° larger than the first predetermined amount of phase shift.
Claim 5
Dependent Claim
41 words
A circuit as in claim 2, in which: the input signal has a predetermined wavelength; the first length is less than approximately one-quarter of the predetermined wavelength; and the second and third lengths are each approximately three-eighths of the predetermined wavelength.
Claim 6
Dependent Claim
24 words
A circuit as in claim 1, in which the first, second and third diodes are heavily doped "P" type-intrinsic-heavily doped "N" type (PIN) diodes.
Claim 7
Dependent Claim
106 words
A circuit as in claim 1, in which the biasing means comprises voltage source means for selectively applying a first bias voltage to the first and second diodes through the first transmission line means and to the third diode through said junction of the second and third transmission line means causing the first, second and third diodes to be forward biased; or applying a second bias voltage to the first and second diodes through the first transmission line means and to the third diode through said junction of the second and third transmission line means causing the first, second and third diodes to be reverse biased.
Claim 8
Dependent Claim
76 words
A circuit as in claim 6, in which: the first transmission line means comprises first and second transmission line segments connected in series with each other between the input and output terminal means, the first and second transmission line segments defining a junction therebetween; and the voltage source means is connected in circuit to selectively apply the first bias voltage or the second bias voltage to said junction of the first and second transmission line segments.
Claim 9
Dependent Claim
58 words
A circuit as in claim 7, in which the biasing means further comprises: first radio frequency choke means coupled between the voltage source means and said junction of the first and second transmission line segments; and second radio frequency choke means coupled between the voltage source means and said junction of the second and third transmission line means.
Claim 10
Dependent Claim
40 words
A circuit as in claim 6, in which the biasing means further comprises: first radio frequency choke means coupled between the input terminal means and ground; and second radio frequency choke means coupled between the output terminal means and ground.
Claim 11
Dependent Claim
57 words
A circuit as in claim 6, in which the biasing means further comprises: first capacitor means connected in series circuit with the second transmission line means between the input terminal means and the third diode; and second capacitor means connected in series with the third transmission line means between the output terminal means and the third diode.
Claim 12
Dependent Claim
50 words
A circuit as in claim 6, in which: the first, second and third diodes each have cathodes and anodes; and the voltage source means is connected in circuit to selectively apply the first bias voltage or the second bias voltage to the cathodes of the first, second and third diodes.
Claim 13
Dependent Claim
50 words
A circuit as in claim 6, in which: the first, second and third diodes each have cathodes and anodes; and the voltage source means is connected in circuit to selectively apply the first bias voltage or the second bias voltage to the anodes of the first, second and third diodes.
Claim 14
Dependent Claim
49 words
A circuit as in claim 1, further comprising an electrically insulating substrate, the input and output terminal means and first, second and third diodes being mounted on the substrate, the first, second and third transmission line means comprising first, second and third microstrip lines respectively formed on the substrate.
Claim 15
Dependent Claim
141 words
A phase bit circuit, comprising: an input terminal; an output terminal; first transmission line means coupled between the input and output terminal means; a first diode coupled between the first transmission line means and the input terminal means; a second diode coupled between the first transmission line means and the output terminal means; second and third transmission line means connected in series with each other between the input and output terminal means, the second and third transmission line means defining a junction therebetween; a third diode coupled between said junction of the second and third transmission line means and ground; and circuit means coupled to the first, second and third diodes for selectively applying a first bias voltage for forward biasing the first, second and third diodes; or a second bias voltage for reverse biasing the first, second and third diodes.
Claim 16
Dependent Claim
141 words
A phase bit circuit, comprising: an input terminal; an output terminal; first transmission line means coupled between the input and output terminal means; a first diode coupled between the first transmission line means and the input terminal means; a second diode coupled between the first transmission line means and the output terminal means; second and third transmission line means connected in series with each other between the input and output terminal means, the second and third transmission line means defining a junction therebetween; a third diode coupled between said junction of the second and third transmission line means and ground; and circuit means coupled to the first, second and third diodes for selectively applying a first bias voltage for forward biasing the first, second and third diodes; or a second bias voltage for reverse biasing the first, second and third diodes.
Claim 17
Dependent Claim
56 words
A circuit as in claim 14, in which the first, second and third transmission line means have first, second and third lengths respectively, the sum of the second and third lengths being larger than the first length such that the second predetermined amount of phase shift is larger than the first predetermined amount of phase shift.
Claim 18
Dependent Claim
41 words
A circuit as in claim 14, in which: the input signal has a predetermined wavelength; the first length is less than approximately one-quarter of the predetermined wavelength; and the second and third lengths are each approximately three-eighths of the predetermined wavelength.
Claim 19
Dependent Claim
24 words
A circuit as in claim 14, in which the first, second and third diodes are heavily doped "P" type-intrinsic-heavily doped "N" type (PIN) diodes.
Claim 20
Dependent Claim
106 words
A circuit as in claim 14, in which the circuit means comprises voltage source means for selectively applying the first bias voltage to the first and second diodes through the first transmission line means and to the third diode through said junction of the second and third transmission line means causing the first, second and third diodes to be forward biased; or applying the second bias voltage to the first and second diodes through the first transmission line means and to the third diode through said junction of the second and third transmission line means causing the first, second and third diodes to be reverse biased.
Claim 21
Dependent Claim
76 words
A circuit as in claim 18, in which: the first transmission line means comprises first and second transmission line segments connected in series with each other between the input and output terminal means, the first and second transmission line segments defining a junction therebetween; and the voltage source means is connected in circuit to selectively apply the first bias voltage or the second bias voltage to said junction of the first and second transmission line segments.
Claim 22
Dependent Claim
83 words
A circuit as in claim 19, in which the circuit means further comprises: first radio frequency choke means coupled between the voltage source means and said junction of the first and second transmission line segments; second radio frequency choke means coupled between the voltage source means and said junction of the second and third transmission line means; first radio frequency choke means coupled between the input terminal means and ground; second radio frequency choke means coupled between the output terminal means and ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-03 | 1996-11-02 | 1997-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-03 | 2000-11-02 | 2001-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-03 | 2004-11-02 | 2005-05-04 | $7700.00 | Window Closed / Lapsed |