Mos semiconductor device having a surge protecting element

Claim 2

A MOS semiconductor device having a surge protecting circuit, comprising: a semiconductor substrate having a major surface; a plurality of electrodes overlying said major surface; a MOS circuit in said major surface; a bidirectional semiconductor surge absorber, coupled between the gate of said MOS circuit and a reference one of said electrodes contacting said major surface of the substrate; and a bidirectional Zener diode connected in series with said bidirectional semiconductor surge absorber.

Claim 3

The MOS semiconductor device of claim 1, wherein said semiconductor substrate further includes a bottom surface opposite and spaced from said major surface, further comprising at least one electrode on said bottom surface.

Claim 4

The MOS semiconductor device of claim 1, wherein said bidirectional Zener diode includes at least two regions of different conductivity types.

Claim 5

The MOS semiconductor device of claim 1, wherein said semiconductor substrate includes: a first semiconductor layer of a first conductivity type adjacent said major surface; one or more first regions of a second conductivity type selectively in the surface of said semiconductor layer, said second conductivity type being different from the first conductivity type; and one or more second regions of the first conductivity type being selectively in the surface of said first region.

Claim 6

The MOS semiconductor device of claim 4, wherein said reference electrode contacts said first and second regions.

Claim 7

The MOS semiconductor device of claim 4, wherein the impurity concentration of said second regions is greater than that of said first semiconductor layer.

Claim 8

The MOS semiconductor device of claim 4, further comprising a gate insulating film at least partially on said first region and an exposed portion of said semiconductor layer.

Claim 9

The MOS semiconductor device of claim 7, further comprising a gate on said gate insulating film.

Claim 10

The MOS semiconductor device of claim 4, further comprising an insulating layer at least partially on said first region and an exposed portion of said first semiconductor layer.

Claim 11

The MOS semiconductor device of claim 9, wherein said bidirectional semiconductor surge absorber is on said insulating layer.

Claim 12

The MOS semiconductor device of claim 9, wherein said bidirectional Zener diode is on said insulating layer.

Claim 13

A MOS semiconductor device having a surge protecting circuit, comprising: a semiconductor substrate having a major surface, wherein said semiconductor substrate includes, a first semiconductor layer of a first conductivity type adjacent said major surface; one or more first regions of a second conductivity type selectively in the surface of said first semiconductor layer, said second conductivity type being different from the first conductivity type; and one or more second regions of the first conductivity type being selectively in the surface of said first region; a plurality of electrodes overlying said major surface; a MOS circuit in said major surface; and a bidirectional semiconductor surge absorber, coupled between the gate of said MOS circuit and a reference one of said electrodes contacting said major surface of the substrate, wherein said reference electrode contacts said first and second regions.

Claim 14

A MOS semiconductor device having a surge protecting circuit, comprising: a semiconductor substrate having a major surface, wherein said semiconductor substrate includes, a first semiconductor layer of a first conductivity type adjacent said major surface; one or more first regions of a second conductivity type selectively in the surface of said first semiconductor layer, said second conductivity type being different from the first conductivity type; and one or more second regions of the first conductivity type being selectively in the surface of said first region; a plurality of electrodes overlying said major surface; a MOS circuit in said major surface; and a bidirectional semiconductor surge absorber, coupled between the gate of said MOS circuit and a reference one of said electrodes contacting said major surface of the substrate, wherein said reference electrode contacts said first and second regions.

Claim 15

A MOS semiconductor device having a surge protecting circuit, comprising: a semiconductor substrate having a major surface; a plurality of electrodes overlying said major surface; a MOS circuit in said major surface; a bidirectional semiconductor surge absorber, coupled between the gate of said MOS circuit and a reference one of said electrodes contacting said major surface of the substrate, wherein said bidirectional semiconductor surge absorber includes, a first semiconductor layer of a first conductivity type overlying said major surface; one or more base regions of a second conductivity type selectively throughout the said first semiconductor layer, said second conductivity type being different from the first conductivity type; and one or more diffusion regions of the first conductivity type selectively formed in the surface of said base region.

Claim 16

A MOS semiconductor device having a surge protecting circuit, comprising: a semiconductor substrate having a major surface; a plurality of electrodes overlying said major surface; a MOS circuit in said major surface; a bidirectional semiconductor surge absorber, coupled between the gate of said MOS circuit and a reference one of said electrodes contacting said major surface of the substrate, wherein said bidirectional semiconductor surge absorber includes, a first semiconductor layer of a first conductivity type overlying said major surface; one or more base regions of a second conductivity type selectively throughout the said first semiconductor layer, said second conductivity type being different from the first conductivity type; and one or more diffusion regions of the first conductivity type selectively formed in the surface of said base region.

Claim 17

The MOS semiconductor device of claim 13, wherein the impurity concentration of said diffusion region is greater than that of said first semiconductor layer.

Claim 18

The MOS semiconductor device of claim 13, wherein said reference electrode contacts one base region and one diffusion region adjacent to said one base region.

Claim 19

The MOS semiconductor device of claim 13, wherein said semiconductor substrate further includes a bottom surface opposite and spaced from said major surface, further comprising at least one electrode on said bottom surface.

Claim 20

The MOS semiconductor device of claim 13, wherein said semiconductor substrate includes: a second semiconductor layer of a first conductivity type adjacent said major surface; one or more first regions of a second conductivity type selectively in the surface of said second semiconductor layer, said second conductivity type being different from the first conductivity type; and one or more second regions of the first conductivity type being selectively in the surface of said first region.

Claim 21

The MOS semiconductor device of claim 17, wherein said reference electrode contacts said first and second regions of said second semiconductor layer.

Claim 22

The MOS semiconductor device of claim 17, wherein the impurity concentration of said second regions is greater than that of said second semiconductor layer.

Claim 23

The MOS semiconductor device of claim 17, further comprising an insulating film at least partially on said first region and an exposed portion of said second semiconductor layer.

Claim 24

The MOS semiconductor device of claim 20, further comprising a gate on said insulating film.

Claim 25

The MOS semiconductor device of claim 21, further comprising a gate electrode, wherein said gate electrode contacts a second base region and one diffusion region adjacent to said second base region, said gate electrode being connected to said gate.

Claim 26

The MOS semiconductor device of claim 17, further comprising an insulating layer at least partially on said first region and an exposed portion of said second semiconductor layer.

Claim 27

The MOS semiconductor device of claim 23, wherein said bidirectional semiconductor surge absorber is one said insulating layer.

Claim 28

A MOS semiconductor device of claim 13, further comprising a bidirectional Zener diode connected in series with said bidirectional semiconductor surge absorber.

Claim 29

The MOS semiconductor device of claim 25, wherein said semiconductor substrate further includes a bottom surface opposite and spaced from said major surface, further comprising at least one electrode on said bottom surface.

Claim 30

The MOS semiconductor device of claim 25, wherein said bidirectional Zener diode includes at least two regions of different conductivity types.

Claim 31

The MOS semiconductor device of claim 25, wherein said semiconductor substrate includes: a second semiconductor layer of a first conductivity type adjacent said major surface; one or more first regions of a second conductivity type selectively in the surface of said second semiconductor layer, said second conductivity type being different from the first conductivity type; and one or more second regions of the first conductivity type being selectively in the surface of said first region.

Claim 32

The MOS semiconductor device of claim 28, wherein said reference electrode contacts said first and second regions.

Claim 33

The MOS semiconductor device of claim 28, wherein the impurity concentration of said second regions is greater than that of said second semiconductor layer.

Claim 34

The MOS semiconductor device of claim 28, further comprising an insulating film at least partially on said first region and an exposed portion of said second semiconductor layer.

Claim 35

The MOS semiconductor device of claim 31, further comprising a gate on said insulating film.

Claim 36

The MOS semiconductor device of claim 28, further comprising an insulating layer at least partially on said first region and an exposed portion of said second semiconductor layer.

Claim 37

The MOS semiconductor device of claim 33, wherein said bidirectional semiconductor surge absorber is on said insulating layer.

Claim 38

The MOS semiconductor device of claim 33, wherein said bidirectional Zener diode is on said insulating layer.