US5204790A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital signal recording circuit for digital video cassette tape recorder
Assignee: Samsung Electronics Co Ltd
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Filing: 1991-02-27
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Granted: 1993-04-20
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Expires: 2011-02-27
Abstract
Abstract A digital signal recording circuit compensates for the deterioration of a digital signal that occurs during recording and reduces the occurrence of bit errors during playback in a digital signal recording and playback apparatus. The circuit includes a read/write circuit which records and reads digital signals to and from a recording medium and which relays its data to a playback circuit for reproducing digital signals read from the recording medium. The circuit also provides an input signal processing circuit which converts along signals into processed digital signals for recording and a compensation circuit which both amplifies the digital signal for recording and compensates for bit deterioration caused by frequency variations in the processed digital signals.
Inventors
- 👤 Chang-jin Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:22
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B5/00; G11B5/02; G11B5/09; G11B20/10009; G11B20/10527
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
60 words
A digital signal recording circuit, comprising: recording signal generating means for converting an input signal into a digital signal of a format appropriate for recording on a recording medium; equalization means for compensating deterioration in said digital signal caused by frequency variations thereof; and read/write means for recording a compensated digital signal from said equalization means onto a recording medium.
Claim 2
Dependent Claim
60 words
A digital signal recording circuit, comprising: recording signal generating means for converting an input signal into a digital signal of a format appropriate for recording on a recording medium; equalization means for compensating deterioration in said digital signal caused by frequency variations thereof; and read/write means for recording a compensated digital signal from said equalization means onto a recording medium.
Claim 3
Dependent Claim
46 words
A digital signal recording circuit according to claim 1, wherein said read/write means further reads recorded digital signals from a recording medium, said circuit further comprising: playback means for processing digital signals read by said read/write means into output signals for application to an output circuit.
Claim 4
Dependent Claim
72 words
A digital signal recording circuit according to claim 1, wherein said equalization means comprises: amplifier means for wave-shaping and amplifying the digital signal from said recording signal generating means; compensation means for generating a compensation signal as a function of frequency variations of said digital signal from said recording signal generating means; and summing means for developing said compensated digital signal by combining outputs of said amplifier means and said compensation means.
Claim 5
Dependent Claim
56 words
A digital signal recording circuit according to claim 3, wherein said amplifier means comprises: a comparator for wave-shaping the digital signal output of said recording signal generating means; a constant current source for generating a current of a predetermined level; and a differential amplifier for amplifying an output of said comparator using said constant current source.
Claim 6
Dependent Claim
33 words
A digital signal recording circuit according to claim 4, wherein said comparator wave-shapes said digital signal output of said recording signal generating means by comparing said digital signal output with a reference voltage.
Claim 7
Dependent Claim
40 words
A digital signal recording circuit according to claim 3, wherein said compensation means comprises: a frequency-to-voltage (F/V) converter for converting frequency variations of said digital signal from said recording signal generating means into voltage variations to generate said compensation signal.
Claim 8
Dependent Claim
60 words
A digital signal recording circuit according to claim 3, wherein said summing means comprises a transformer having primary and secondary windings, the output of said amplifier means being connected across said primary winding and the output of said compensation means being connected to a center tap on said primary winding, and said secondary winding is connected to said read/write means.
Claim 9
Dependent Claim
67 words
A digital signal recording circuit according to claim 7, wherein said amplifier means comprises: a comparator for wave-shaping the digital signal output of said recording signal generating means; a constant current source for generating a current of a predetermined level; and a differential amplifier for amplifying an output of said comparator using said constant current source, and applying the result across said primary winding of said transformer.
Claim 10
Dependent Claim
33 words
A digital signal recording circuit according to claim 8, wherein said comparator wave-shapes said digital signal output of said recording signal generating means by comparing said digital signal output with a reference voltage.
Claim 11
Dependent Claim
56 words
A digital signal recording circuit according to claim 9, wherein said compensation means comprises: a frequency-to-voltage (F/V) converter for converting frequency variations of said digital signal from said recording signal generating means into voltage variations to generate said compensation signal, and applying said compensation signal to the center tap of said primary winding of said transformer.
Claim 12
Dependent Claim
46 words
A digital signal recording circuit according to claim 10, wherein said read/write means further reads recorded digital signals from a recording medium, said circuit further comprising: playback means for processing digital signals read by said read/write means into output signals for application to an output circuit.
References Cited (Backward Citations)
US4367495A
Cited
US4635140A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |