Video signal processing apparatus for restoring an interlaced video signal stored in a memory

Claim 2

A video signal processing apparatus comprising: a) A memory capable of storing at least an (n+1) horizontal scanning line portion of an interlaced video signal having (2n+1) horizontal scanning lines for one frame which consists of two fields, n being an integer: b) input means arranged to supply the interlaced video signal to said memory: c) writing address control means for controlling a writing address of said memory, said writing address control means being arranged to reset the writing address of said memory in response to a front edge of a vertical synchronizing signal included in the interlaced video signal received by said input means so that a head portion of the vertical synchronizing signal is written at a first address immediately after the resetting of the writing address; and d) reading address control means for controlling a reading address of said memory, said reading address control means being arranged to reset the reading address of said memory alternately at an interval of n horizontal scanning periods and at an interval of (n+1) horizontal scanning periods.

Claim 3

An apparatus according to claim 1, further comprising writing/reading switching means for switching said memory between a writing state and a reading state, said writing/reading switching means being arranged to change said memory from the writing state over to the reading state offer the lapse of (n+1) horizontal scanning periods from resetting of the writing address of said memory by said writing address control means.

Claim 4

An apparatus according to claim 2, wherein said writing address control means and said reading address control means include a common address counter, the writing and reading addresses of said memory being arranged to be determined by an output of said address counter.

Claim 5

An apparatus according to claim 3, wherein said writing address control means is arranged to inhibit an address cleared state of said address counter in response to a front edge of a first vertical synchronizing signal included in the interlaced video signal received immediately after an instruction of writing the interlaced video signal to said memory.

Claim 6

An apparatus according to claim 3, wherein said reading address control means includes first detecting means arranged to produce a first detection pulse indicative of the lapse of the (n+1) horizontal scanning periods after an address of said address counter is reset, said reading address control means being arranged to reset said address counter by using said first detection pulse.

Claim 7

An apparatus according to claim 5, wherein said reading address control means includes second detecting means arranged to produce a second detection pulse indicative of the lapse of n horizontal scanning periods after the address of said address counter is reset by using said first detection pulse, said reading address control means being arranged further to reset said address counter by using said second detection pulse.

Claim 8

An apparatus according to claim 5, wherein said writing/reading switching means is arranged to change said memory from the writing state over to the reading state in response to said first detection pulse when said first detection pulse is first obtained after the writing address of said memory is reset by said writing address control means.

Claim 9

A video signal reproducing apparatus comprising: a) reproducing means for reproducing from a recording medium an interlaced video signal having (2n+1) horizontal scanning lines for each frame which consists of two fields, a being an integer; b) a memory arranged to receive the video signal reproduced by said reproducing means and capable of storing at least an (n+1) horizontal scanning line portion of the video signal: c) writing address control means for controlling a writing address of said memory, said writing address control means being arranged to reset the writing address of said memory in response to a front edge of a vertical synchronizing signal included in the interlaced video signal reproduced by said reproducing means so that a head portion of the vertical synchronizing signal is written at a first address immediately after the resetting of the writing address; and d) reading address control means for controlling a reading address of said memory, said reading address control means being arranged to reset the reading address to said memory alternately at an interval of n horizontal scanning periods and at an interval of (n+1) horizontal scanning periods.

Claim 10

A video signal reproducing apparatus comprising: a) reproducing means for reproducing from a recording medium an interlaced video signal having (2n+1) horizontal scanning lines for each frame which consists of two fields, a being an integer; b) a memory arranged to receive the video signal reproduced by said reproducing means and capable of storing at least an (n+1) horizontal scanning line portion of the video signal: c) writing address control means for controlling a writing address of said memory, said writing address control means being arranged to reset the writing address of said memory in response to a front edge of a vertical synchronizing signal included in the interlaced video signal reproduced by said reproducing means so that a head portion of the vertical synchronizing signal is written at a first address immediately after the resetting of the writing address; and d) reading address control means for controlling a reading address of said memory, said reading address control means being arranged to reset the reading address to said memory alternately at an interval of n horizontal scanning periods and at an interval of (n+1) horizontal scanning periods.

Claim 11

A video signal processing apparatus comprising: a) a memory capable of storing a larger portion than one field portion of an interlaced video signal; b) input means arranged to supply the interlaced video signal to said memory; c) writing address control means for controlling a writing address of said memory so that a head portion of a vertical synchronizing signal of the interlaced video signal is written at a first address immediately after resetting the writing address; and d) reading address control means for controlling a reading address of said memory so that a larger portion than the one field portion of the interlaced video signal and a smaller portion than the one field portion of the interlaced video signal are alternately read out from said memory.

Claim 12

A video signal processing apparatus comprising: a) a memory capable of storing a larger portion than one field portion of an interlaced video signal; b) input means arranged to supply the interlaced video signal to said memory; c) writing address control means for controlling a writing address of said memory so that a head portion of a vertical synchronizing signal of the interlaced video signal is written at a first address immediately after resetting the writing address; and d) reading address control means for controlling a reading address of said memory so that a larger portion than the one field portion of the interlaced video signal and a smaller portion than the one field portion of the interlaced video signal are alternately read out from said memory.

Claim 13

An apparatus according to claim 9, wherein said interlaced video signal has (2n+1) horizontal scanning lines for one frame which consists of two fields, n being an integer, and said reading address control means is arranged to reset the reading address of said memory alternately at an interval of n horizontal scanning periods and at an interval of (n+1) horizontal scanning periods.

Claim 14

An apparatus according to claim 10, wherein said memory is able to store at least an (n+1) horizontal scanning line portion of the interlaced video signal.

Claim 15

A video signal processing apparatus comprising: a) a memory capable of storing a larger portion than one field portion of an interlaced video signal: b) input means arranged to supply the interlaced video signal to said memory: c) writing address control means for controlling a writing address of said memory so that two head portions of vertical synchronizing signals of the interlaced video signal are written in said memory; and d) reading address control means for controlling a reading address of said memory, said reading address control means being arranged to reset the reading address of said memory so that a portion including the two head portions of vertical synchronizing signals and a portion including zero or only one head portion of a vertical synchronizing signal are alternately read out from said memory.

Claim 16

A video signal processing apparatus comprising: a) a memory capable of storing a larger portion than one field portion of an interlaced video signal: b) input means arranged to supply the interlaced video signal to said memory: c) writing address control means for controlling a writing address of said memory so that two head portions of vertical synchronizing signals of the interlaced video signal are written in said memory; and d) reading address control means for controlling a reading address of said memory, said reading address control means being arranged to reset the reading address of said memory so that a portion including the two head portions of vertical synchronizing signals and a portion including zero or only one head portion of a vertical synchronizing signal are alternately read out from said memory.