US5204554A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Partial isolation of power rails for output buffer circuits
Assignee: Fairchild Semiconductor Corp
•
Filing: 1991-12-06
•
Granted: 1993-04-20
•
Expires: 2011-12-06
Abstract
Abstract An output buffer circuit (10) delivers output signals of high and low potential levels at an output (V OUT ) in response to data signals at an input (V IN ). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (V CCQ ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (V CCN ) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (V CCQ , V CCN ) for reducing V CC droop in the relatively noisy supply rail (V CCN ) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (V OUT ). A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN). The coupling resistors (R5 and R5A) have low resistance values selected for partially coupling the supply and ground rails respectively, while maintaining partial isolation for protecting input dynamic threshold levels of quiet outputs. The first coupling resistor (R5) is coupled between supply rail bond pads (20,22), while the second coupling resistor (R5A) is coupled between ground rail bond pads (30,32). The power rail bond pads (20,22) (30,32) are coupled respectively to split leads (24,25) (34,35) of a split lead leadframe merging respectively to a common V CC pin (28) and a common GND pin (38).
Inventors
- 👤 James R. Ohannes
- 👤 Stephen W. Clukey
- 👤 E. David Haacke
- 👤 Roy L. Yarbrough
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:03
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K17/00; H03K17/16; H10; H10W; H10W72/00; H10W72/50; H10W72/541; H10W72/5445
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
132 words
A power rail coupling for an output buffer circuit having an output coupled to a common bus with other output buffer circuits, said output buffer circuit having relatively quiet and relatively noisy power supply rails coupled respectively to input and output stages of the output buffer circuit comprising: a first coupling resistor coupled between the relatively quiet and noisy power supply rails and having a low resistance value selected for partially coupling said supply rails to reduce crash on the noisy power supply rail and thereby reduce output step in voltage during low to high transitions at the output, said first coupling resistor partially isolating said relatively quiet and noisy power supply rails to maintain input dynamic threshold voltage levels of other non-switching quiet output buffer circuits coupled to the common bus.
Claim 2
Dependent Claim
132 words
A power rail coupling for an output buffer circuit having an output coupled to a common bus with other output buffer circuits, said output buffer circuit having relatively quiet and relatively noisy power supply rails coupled respectively to input and output stages of the output buffer circuit comprising: a first coupling resistor coupled between the relatively quiet and noisy power supply rails and having a low resistance value selected for partially coupling said supply rails to reduce crash on the noisy power supply rail and thereby reduce output step in voltage during low to high transitions at the output, said first coupling resistor partially isolating said relatively quiet and noisy power supply rails to maintain input dynamic threshold voltage levels of other non-switching quiet output buffer circuits coupled to the common bus.
Claim 3
Dependent Claim
38 words
The power rail coupling of claim 1 wherein the relatively quiet and noisy power supply rails are coupled respectively to spaced apart bond pads, and wherein the first coupling resistor is coupled between said supply rail bond pads.
Claim 4
Dependent Claim
119 words
The power rail coupling of claim 1 wherein the output buffer circuit comprises relatively quiet and relatively noisy power ground rails coupled respectively to said input and output stages of the output buffer circuit, and further comprising: a second coupling resistor coupled between the relatively quiet and noisy power ground rails and having a low resistance value selected for partially coupling said ground rails to reduce ground bounce on the noisy ground rail and thereby reduce output step in voltage during high to low transition at the output, said second coupling resistor partially isolating said relatively quiet and noisy ground rails to maintain input dynamic threshold levels for other non-switching quiet output buffer circuits coupled to the common bus.
Claim 5
Dependent Claim
38 words
The power rail coupling of claim 3 wherein the relatively quiet and noisy power ground rails are coupled to respective spaced apart bond pads and wherein said second coupling resistor is coupled between said ground rail bond pads.
Claim 6
Dependent Claim
29 words
The output buffer circuit of claim 2 wherein the power supply rail bond pads are coupled to split leads of a split lead leadframe merging to a common pin.
Claim 7
Dependent Claim
23 words
The output buffer circuit of claim 2 wherein the power supply rail bond pads are coupled to separate leadframe fingers of a leadframe.
Claim 8
Dependent Claim
31 words
The power rail coupling of claim 4 wherein the ground rail bond pads are coupled respectively to the split leads of a split lead leadframe merging to a common GND pin.
Claim 9
Dependent Claim
145 words
An output buffer circuit for delivering output signals of high and low potential levels at an output in response to data signals at an input, said output buffer circuit comprising an input stage coupled between a relatively quiet power supply rail and a relatively quiet power ground rail, and an output stage coupled between a relatively noisy power supply rail and a relatively noisy power ground rail, the improvement for reducing droop in the relatively noisy supply rail for reducing output step in voltage during transition from low to high potential level at the output comprising: a first coupling resistor coupled between the relatively quiet and noisy supply rails, said resistor having a low resistance value selected for partially coupling said supply rails while maintaining partial isolation for maintaining input dynamic threshold levels of other non-switching quiet output buffer circuits coupled to a common bus.
Claim 10
Dependent Claim
145 words
An output buffer circuit for delivering output signals of high and low potential levels at an output in response to data signals at an input, said output buffer circuit comprising an input stage coupled between a relatively quiet power supply rail and a relatively quiet power ground rail, and an output stage coupled between a relatively noisy power supply rail and a relatively noisy power ground rail, the improvement for reducing droop in the relatively noisy supply rail for reducing output step in voltage during transition from low to high potential level at the output comprising: a first coupling resistor coupled between the relatively quiet and noisy supply rails, said resistor having a low resistance value selected for partially coupling said supply rails while maintaining partial isolation for maintaining input dynamic threshold levels of other non-switching quiet output buffer circuits coupled to a common bus.
Claim 11
Dependent Claim
59 words
The output buffer circuit of claim 8 comprising a second coupling resistor coupled between the relatively quiet and noisy ground rails, said second coupling resistor having a low resistance value selected for partially coupling said ground rails while maintaining partial isolation for maintaining input dynamic threshold levels for other non-switching quiet output buffer circuits coupled on a common bus.
Claim 12
Dependent Claim
37 words
The output buffer circuit of claim 8 wherein the relatively quiet and noisy supply rails are coupled to respective spaced apart bond pads and wherein the first coupling resistor is coupled between said supply rail bond pads.
Claim 13
Dependent Claim
38 words
The output buffer circuit of claim 9 wherein the relatively quiet and noisy power ground rails are coupled to respective spaced apart bond pads and wherein the second coupling resistor is coupled between said ground rail bond pads.
Claim 14
Dependent Claim
29 words
The output buffer circuit of claim 9 wherein the supply rail bond pads are coupled respectively to split leads of a split lead leadframe merging to a common pin.
Claim 15
Dependent Claim
30 words
The output buffer circuit of claim 11 wherein the ground rail bond pads are coupled respectively to split leads of a split lead leadframe merging at a common GND pin.
Claim 16
Dependent Claim
128 words
A power rail coupling for an output buffer circuit having an output coupled to a common bus with other output buffer circuits, said output buffer circuit having relatively quiet and relatively noisy power ground rails coupled respectively to input and output stages of the output buffer circuit comprising: a coupling resistor coupled between the relatively quiet and noisy power ground rails and having a low resistance value selected for partially coupling said ground rails to reduce ground bounce on the noisy power ground rail thereby reducing output step in voltage during high to low transition at the output, said coupling resistor partially isolating said relatively quiet and noisy ground rails to maintain input dynamic threshold levels for other non-switching quiet output buffer circuits coupled to the common bus.
Claim 17
Dependent Claim
128 words
A power rail coupling for an output buffer circuit having an output coupled to a common bus with other output buffer circuits, said output buffer circuit having relatively quiet and relatively noisy power ground rails coupled respectively to input and output stages of the output buffer circuit comprising: a coupling resistor coupled between the relatively quiet and noisy power ground rails and having a low resistance value selected for partially coupling said ground rails to reduce ground bounce on the noisy power ground rail thereby reducing output step in voltage during high to low transition at the output, said coupling resistor partially isolating said relatively quiet and noisy ground rails to maintain input dynamic threshold levels for other non-switching quiet output buffer circuits coupled to the common bus.
Claim 18
Dependent Claim
36 words
The power rail circuit of claim 14 wherein the relatively quiet and noisy ground rails are coupled to respective spaced apart bond pads and wherein the coupling resistor is coupled between said ground rail bond pads.
Claim 19
Dependent Claim
30 words
The power rail circuit of claim 15 wherein the ground rail bond pads are coupled respectively to split leads of a split lead leadframe merging at a common GND pin.
Claim 20
Dependent Claim
172 words
An output buffer circuit for delivering output signals of high and low potential levels at an output in response to data signals at an input, said output buffer circuit comprising an input stage coupled between a relatively quiet power supply rail and a relatively quiet power ground rail, and an output stage coupled between a relatively noisy power supply rail and a relatively noisy power ground rail, the improvement for reducing droop in the relatively noisy supply rail for reducing output step in voltage during transition from low to high potential level at the output comprising: a coupling resistor coupled between the relatively quiet and noisy ground rails, said coupling resistor having a low resistance value selected for partially coupling said ground rails to reduce ground bounce and thereby reduce output step in voltage during high to low transitions at the output, said coupling resistor partially isolating the relatively quiet and noisy ground rails for maintaining input dynamic threshold levels for other non-switching quiet output buffer circuits coupled to a common bus.
Claim 21
Dependent Claim
172 words
An output buffer circuit for delivering output signals of high and low potential levels at an output in response to data signals at an input, said output buffer circuit comprising an input stage coupled between a relatively quiet power supply rail and a relatively quiet power ground rail, and an output stage coupled between a relatively noisy power supply rail and a relatively noisy power ground rail, the improvement for reducing droop in the relatively noisy supply rail for reducing output step in voltage during transition from low to high potential level at the output comprising: a coupling resistor coupled between the relatively quiet and noisy ground rails, said coupling resistor having a low resistance value selected for partially coupling said ground rails to reduce ground bounce and thereby reduce output step in voltage during high to low transitions at the output, said coupling resistor partially isolating the relatively quiet and noisy ground rails for maintaining input dynamic threshold levels for other non-switching quiet output buffer circuits coupled to a common bus.
Claim 22
Dependent Claim
59 words
The output buffer circuit of claim 17 comprising a second coupling resistor coupled between the relatively quiet and noisy supply rails, said second coupling resistor having a low resistance value selected for partially coupling said supply rails while maintaining partial isolation for protecting input dynamic threshold levels for other non-switching quiet output buffer circuits coupled on a common bus.
Claim 23
Dependent Claim
38 words
The output buffer circuit of claim 17 wherein the relatively quiet and noisy power ground rails are coupled to respective spaced apart bond pads and wherein the second coupling resistor is coupled between said ground rail bond pads.
Claim 24
Dependent Claim
30 words
The output buffer circuit of claim 19 wherein the ground rail bond pads are coupled respectively to split leads of a split lead leadframe merging at a common GND pin.
References Cited (Backward Citations)
JPS57164548A
Cited
EP0214307A1
Cited
US5065224A
Cited
US4855863A
Cited
US5049763A
Cited
US5121036A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |