US5202761A
Expired / Lapsed
US
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Audio synchronization apparatus
Assignee: Technology Licensing Corp
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Filing: 1991-05-28
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Granted: 1993-04-13
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Expires: 2011-05-28
Abstract
Abstract An audio synchronizer apparatus having a delay detector for accurately measuring the delay of a video apparatus, coupled with a controllable, variable delay audio delay circuit for accurately delaying an audio frequency signal by substantially the same amount as the video signal delay. The apparatus disclosed can operate successfully even with video delays exceeding one frame, without requiring an auxiliary correlation circuit. The variable audio delay may also contain precise filtering to compensate for adverse effects introduced by the delay.
Inventors
- 👤 J. Carl Cooper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:21
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073; H04N5/44; H04N5/60
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
172 words
An apparatus for equilizing video to audio frequency signal timing in a television system of the type having a video signal processing path separate from the audio path, and having a video processing circuit having an input and an output, comprising: an audio write address circuit responsive to the timing of the video input to said video processing circuit for generating an audio write address signal; an audio read address circuit responsive to the timing of the video output from said video processing circuit for generating an audio read address signal; a digital audio memory responsive to said audio read address signal and to said audio write address signal and having an input and an output; an analog to digital converter having an input responsive to an analog audio signal and having an output compatible with and communicating with the input of the audio memory, and; a digital to analog converter responsive to the output of said digital audio memory for converting the output of said digital audio memory to analog signals.
Claim 2
Independent Claim
172 words
An apparatus for equilizing video to audio frequency signal timing in a television system of the type having a video signal processing path separate from the audio path, and having a video processing circuit having an input and an output, comprising: an audio write address circuit responsive to the timing of the video input to said video processing circuit for generating an audio write address signal; an audio read address circuit responsive to the timing of the video output from said video processing circuit for generating an audio read address signal; a digital audio memory responsive to said audio read address signal and to said audio write address signal and having an input and an output; an analog to digital converter having an input responsive to an analog audio signal and having an output compatible with and communicating with the input of the audio memory, and; a digital to analog converter responsive to the output of said digital audio memory for converting the output of said digital audio memory to analog signals.
Claim 3
Independent Claim
254 words
An apparatus for equilizing video to audio frequency signal timing in a television system of the type having separate audio and video signal processing paths and having a video processing circuit having an input to which an input video signal is applied and an output at which an output video signal is produced, comprising: a pulse encoder responsive to preselected characteristics of said input video for generating a timing pulse having characteristics suitable for adding to said video signal, said timing pulse being representative of the occurrence of a preselected characteristic in a video frame, said pulse encoder including a video summer responsive to said input video and the output of said pulse encoder for adding said timing pulse to said input video, said video and pulse combination appearing at the output of said video processing circuit after a delay time; a pulse decoder responsive to the presence of the timing pulse at the output of the video processing circuit; audio read address generator responsive to the pulse decoder output signal for generating an audio read address signal; a digital audio memory responsive to said audio read address signal and to an audio write address signal and having an input and an output; an analog to digital converter having an input responsive to audio signals and having an output compatible with the input of said digital audio memory; a digital to analog converter responsive to the output of said digital audio memory for converting the output of said digital audio memory to analog signals.
Claim 4
Independent Claim
254 words
An apparatus for equilizing video to audio frequency signal timing in a television system of the type having separate audio and video signal processing paths and having a video processing circuit having an input to which an input video signal is applied and an output at which an output video signal is produced, comprising: a pulse encoder responsive to preselected characteristics of said input video for generating a timing pulse having characteristics suitable for adding to said video signal, said timing pulse being representative of the occurrence of a preselected characteristic in a video frame, said pulse encoder including a video summer responsive to said input video and the output of said pulse encoder for adding said timing pulse to said input video, said video and pulse combination appearing at the output of said video processing circuit after a delay time; a pulse decoder responsive to the presence of the timing pulse at the output of the video processing circuit; audio read address generator responsive to the pulse decoder output signal for generating an audio read address signal; a digital audio memory responsive to said audio read address signal and to an audio write address signal and having an input and an output; an analog to digital converter having an input responsive to audio signals and having an output compatible with the input of said digital audio memory; a digital to analog converter responsive to the output of said digital audio memory for converting the output of said digital audio memory to analog signals.
Claim 5
Dependent Claim
20 words
The apparatus as claimed in claim 2 wherein said timing pulse is responsive to vertical sync of said input video.
Claim 6
Dependent Claim
20 words
The apparatus as claimed in claim 2 wherein said timing pulse is responsive to horizontal sync of said input video.
Claim 7
Dependent Claim
25 words
The device as claimed in claim 2 wherein said timing pulse is added to a known line of the vertical interval of said input video.
Claim 8
Dependent Claim
29 words
The apparatus as claimed in claim 2 wherein said timing pulse is added to every Nth field of said input video where N is an integer greater than 1.
Claim 9
Dependent Claim
57 words
The apparatus as claimed in claim 2 wherein said timing pulse is added to every Nth field of said input video where N is an integer and the value of N times the field period of said input video exceeds the maximum delay that said input video signal can experience in passing through said video processing circuit.
Claim 10
Dependent Claim
68 words
The apparatus as claimed in claim 2 wherein said pulse encoder is partially contained within other video processing equipment and encodes a timing signal on said input video signal with said timing signal being used as said timing pulse with said pulse encoder responsive to said input video signal to detect the presence of said timing signal as it arrives at said input of said video processing circuit.
Claim 11
Dependent Claim
17 words
The apparatus as claimed in claim 8 wherein said timing signal is a vertical interval test signal.
Claim 12
Dependent Claim
15 words
The apparatus as claimed in claim 8 wherein said timing signal is a time code.
Claim 13
Dependent Claim
15 words
The apparatus as claimed in claim 8 wherein said timing signal is a DAXI code.
Claim 14
Dependent Claim
32 words
The apparatus as claimed in claim 8 wherein said timing signal is a code having a unique pattern for each of multiple frames of said input video to said video processing circuit.
Claim 15
Dependent Claim
32 words
The apparatus as claimed in claim 2 wherein said pulse decoder is responsive to said video output signal from said video processing circuit to detect the presence of said timing pulse thereon.
Claim 16
Dependent Claim
28 words
The apparatus as claimed in claim 13 wherein said pulse decoder compares said input video and timing pulse combination output from said video processing circuit to a reference.
Claim 17
Dependent Claim
26 words
The apparatus as claimed in claim 14 wherein said reference is responsive to said input video and timing pulse combination output from said video processing circuit.
Claim 18
Dependent Claim
30 words
The apparatus as claimed in claim 13 wherein said pulse decoder is responsive to vertical sync of said input video and timing pulse combination output from said video processing circuit.
Claim 19
Dependent Claim
30 words
The apparatus as claimed in claim 13 wherein said pulse decoder is responsive to horizontal sync of said input video and timing pulse combination output from said video processing circuit.
Claim 20
Dependent Claim
48 words
The apparatus as claimed in claim 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 or 17, wherein said read address generator adjusts said audio read address signal in response to said pulse decoder response to the presence of said timing pulse.
Claim 21
Dependent Claim
23 words
The apparatus as claimed in claim 2 wherein said analog to digital convertor operates with a sample clock responsive to said input video.
Claim 22
Dependent Claim
50 words
The apparatus as claimed in claim 2 including an audio write address circuit comprising a video write address generator for generating a video write address in response to said input video and a write address conditioner for generating said audio write address signal in response to said video write address.
Claim 23
Dependent Claim
51 words
The apparatus as claimed in claim 20 including a write clock generator circuit responsive to said input video for generating a write clock, with said video write address generator responsive to said write clock and wherein said analog to digital convertor operates with a sample clock derived from said write clock.
Claim 24
Dependent Claim
44 words
The apparatus as claimed in claim 2 wherein said audio read address generator includes a video read address generator for generating a video read address, and a read address conditioner for generating said audio read address signal in response to said video read address.
Claim 25
Independent Claim
246 words
An apparatus for equilizing video to audio frequency signal timing in television system of the type having a timing signal encoded onto the video signal, which timing signal is representative of elapsed time from a starting point in an original program until the time of a frame bearing said encoded timing signal, and having separate audio and video signal processing paths and having a video processing path at least part of which includes a delay, comprising: a plurality of timing signal decoders having inputs responsive to said timing signal encoded on said video signal in delayed and undelayed form and each having an output signal which is responsive to said timing signal an audio write address generator responsive to said output signal of said timing signal decoder and responsive to said undelayed video signal for generating a write address signal; an audio read address generator responsive to the output of the timing signal decoder and responsive to delayed video, for generating a read address signal; a digital random access memory responsive to read address signal and to said write address signals, and having an input and an output; an analog to digital converter having an input responsive to analog audio signals and having an output compatible with the input of the digital random access memory, and; a digital to analog converter responsive to the output of said digital random access memory for converting the digital signal of said digital random access memory to an analog signal.
Claim 26
Independent Claim
246 words
An apparatus for equilizing video to audio frequency signal timing in television system of the type having a timing signal encoded onto the video signal, which timing signal is representative of elapsed time from a starting point in an original program until the time of a frame bearing said encoded timing signal, and having separate audio and video signal processing paths and having a video processing path at least part of which includes a delay, comprising: a plurality of timing signal decoders having inputs responsive to said timing signal encoded on said video signal in delayed and undelayed form and each having an output signal which is responsive to said timing signal an audio write address generator responsive to said output signal of said timing signal decoder and responsive to said undelayed video signal for generating a write address signal; an audio read address generator responsive to the output of the timing signal decoder and responsive to delayed video, for generating a read address signal; a digital random access memory responsive to read address signal and to said write address signals, and having an input and an output; an analog to digital converter having an input responsive to analog audio signals and having an output compatible with the input of the digital random access memory, and; a digital to analog converter responsive to the output of said digital random access memory for converting the digital signal of said digital random access memory to an analog signal.
Claim 27
Dependent Claim
32 words
The apparatus as claimed in claim 23 wherein said timing signal is a code having a unique pattern for each of multiple frames of said video input to said video processing circuit.
Claim 28
Dependent Claim
41 words
The apparatus of claim 23 wherein said encoded timing signal is a digital equivalent of the real time of day of said original program and wherein the timing signal decoder is responsive to the real time of day encoded timing signal.
Claim 29
Dependent Claim
28 words
The apparatus of claim 23 wherein said encoded timing signal is the SMPTE time code and wherein said timing signal decoder is responsive to the SMPTE time code.
Claim 30
Dependent Claim
36 words
The apparatus as claimed in claim 23, 24, 25 or 26, wherein said audio read address generator adjusts said audio read address signal in response to said timing signal pulse decoder responding to said timing pulse.
References Cited (Backward Citations)
JPS5452412A
Cited
US4313135A
Cited
US4313135B1
Cited
US4644400A
Cited
US4618890A
Cited
US4703355A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |