US5202643A
Expired / Lapsed
US
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Demodulator for demodulating a π/4-shift DQPSK signal
Assignee: Sony Corp
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Filing: 1992-03-19
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Granted: 1993-04-13
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Expires: 2012-03-19
Abstract
Abstract The present invention is directed to a differential phase-shift keying (PSK) signal demodulator in which an error rate provided when a signal modulated according to a π/4-shift DQPSK modulation system is demodulated can be improved. The differential PSK signal demodulator of the present invention includes means for phase-shifting a phase of a detection reference axis by a predetermined angle each in the counter-clockwise direction in synchronism with a timing at which a symbol to be detected is supplied, wherein the modulated signal is synchronizing-detected such that a rotation angle of the symbol and an angle of a detection reference axis are inhibited from becoming equal to each other, thereby a zero level being prevented from being output as a demodulated output. According to another aspect of the present invention, the differential PSK signal demodulator includes means for judging changing traces of signal points from outputs of an I-axis level discriminating device and a Q-axis level discriminating device to select an optimum path, thus making it possible to reduce a bit error rate (BER).
Inventors
- 👤 Teruo Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:09
CPC Classifications
H; H03; H03D; H03D3/00; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2275; H04L27/2276; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03178; H04L25/03248; H04L25/03273
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
112 words
A differential phase-shift keying (PSK) signal demodulator comprising: (a) a synchronizing detector for synchronizing-detecting a digital modulated signal; (b) a detecting signal generating circuit for generating a plurality of detecting signals whose phases are different by a predetermined angle; (c) a detection signal selecting circuit for selecting one detecting signal from said detecting signal generating circuit and supplying a selected signal to said synchronizing detector as a symbol detecting signal; and (d) a detecting reference axis control circuit for shifting a phase of said detecting signal output from said detecting signal selecting circuit by a predetermined angle each in synchronism with a timing at which a symbol to be detected is supplied.
Claim 2
Dependent Claim
112 words
A differential phase-shift keying (PSK) signal demodulator comprising: (a) a synchronizing detector for synchronizing-detecting a digital modulated signal; (b) a detecting signal generating circuit for generating a plurality of detecting signals whose phases are different by a predetermined angle; (c) a detection signal selecting circuit for selecting one detecting signal from said detecting signal generating circuit and supplying a selected signal to said synchronizing detector as a symbol detecting signal; and (d) a detecting reference axis control circuit for shifting a phase of said detecting signal output from said detecting signal selecting circuit by a predetermined angle each in synchronism with a timing at which a symbol to be detected is supplied.
Claim 3
Dependent Claim
54 words
A differential PSK signal demodulator according to claim 1, wherein said synchronizing detector detects an I-axis level signal and a Q-axis level signal and supplies said detected outputs to a gate circuit so that, when said gate circuit derives a predetermined logic output, then said detecting reference axis is set to an initial phase.
Claim 4
Dependent Claim
31 words
A differential PSK signal demodulator according to claim 2, wherein the phase of said detecting signal output from said detecting signal selecting circuit is shifted by an angle of π/4 each.
Claim 5
Dependent Claim
105 words
A differential PSK signal demodulator according to claim 1, wherein said detecting signal generating circuit for generating a plurality of detecting signals whose phases are shifted by a predetermined angle is composed of a shift register to which a clock signal is supplied, said detecting reference axis control circuit is composed of a counter which resets said detecting reference axis to an initial phase when said gate circuit derives a predetermined logic output and a selector for selecting an output of said shift register in response to an output of said counter and an output selected by said selector is supplied to said synchronizing detector.
Claim 6
Dependent Claim
108 words
A differential phase-shift keying (PSK) signal demodulator comprising: (1) phase rotation amount detecting means for detecting a phase rotation amount from an output of an I/Q synchronizing detector; (2) a path selecting circuit for selecting a path whose likelihood at a plurality of signal points falls within a predetermined range on the basis of the phase rotation amount output from said phase rotation amount detecting means; and (3) a metric storing memory for storing data of said path whose added value of said likelihood at the plurality of signal points falls within a predetermined range, wherein data is demodulated by a read-out output of said metric storing memory.
Claim 7
Dependent Claim
108 words
A differential phase-shift keying (PSK) signal demodulator comprising: (1) phase rotation amount detecting means for detecting a phase rotation amount from an output of an I/Q synchronizing detector; (2) a path selecting circuit for selecting a path whose likelihood at a plurality of signal points falls within a predetermined range on the basis of the phase rotation amount output from said phase rotation amount detecting means; and (3) a metric storing memory for storing data of said path whose added value of said likelihood at the plurality of signal points falls within a predetermined range, wherein data is demodulated by a read-out output of said metric storing memory.
Claim 8
Dependent Claim
29 words
A differential PSK signal demodulator according to claim 5, further comprising a trace state storing memory for storing the path of signal point selected by said path selecting circuit.
References Cited (Backward Citations)
US5128967A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |