Encryption system

Claim 2

An encryption system for providing encrypted digital signal samples from digital signal samples to be encrypted, said system comprising: memory means including a plurality of addressable memory locations for storing said encrypted digital signal samples, an address input for receiving said digital signal samples to be encrypted, and a data port for providing said encrypted digital signal samples responsive to said received digital signal samples; and programming means for providing said memory means with said encrypted digital signal samples, said programming means including addressing means for storing each one of said encrypted digital signal samples at a predetermined unique memory location of said memory means, said programming means comprising a microprocessor having an address output for providing memory means addresses for addressing said memory locations of said memory means and a data output coupled to said memory means data port for providing said memory means with said encrypted digital signal samples.

Claim 3

An encryption system as defined in claim 1 further including a first multiplexer for providing said memory mean address input with either said digital signal samples to be encrypted or said memory means addresses from said microprocessor and a second multiplexer for providing said encrypted digital signal samples from said memory means data port or for providing said memory means data port with said encrypted digital signal samples from said microprocessor.

Claim 4

An encryption system as defined in claim 1 wherein said memory means comprises a random access memory or reprogrammable non-volatile memory such as EEROM, flesh or UVROM.

Claim 5

An encryption system as defined in claim 1 wherein said memory means comprises a reprogrammable non-volatile memory.

Claim 6

An encryption system as defined in claim 1 further including encoder means coupled to said memory means address input for providing said memory means with said digital signal samples to be encrypted.

Claim 7

An encryption system as defined in claim 5 wherein said encoder means comprises a pulse code modulation encoder.

Claim 8

An encryption system as defined in claim 5 wherein said encoder means comprises an adaptive pulse code modulation encoder.

Claim 9

An encryption system as defined in claim 1 further including encoder means coupled to said memory means data port for encoding said encrypted digital signal samples.

Claim 10

An encryption system as defined in claim 8 wherein asid encoder means comprises a pulse code modulation encoder.

Claim 11

An encryption system as defined in claim 8 wherein said encoder means comprises an adaptive pulse code modulation encoder.

Claim 12

A communication system for transmitting and receiving encrypted digital signal samples, said system comprising: generating means for generating digital signal samples to be encrypted; encryption memory means including a first plurality of addressable storage locations for storing said encrypted digital signal samples at predetermined ones of said storage locations, said memory means including an address input for receiving said digital signal samples for addressing said encrypted digital signal samples and a data port for providing said encrypted digital signal samples responsive to said digital signal samples; transmitting means for transmitting said encrypted digital signal samples; receiving means for receiving said encrypted digital signal samples; decryption memory means including a second plurality of addressable storage locations for storing said digital signal samples at storage locations complimentary to said encrypted digital signal sample storage locations of said encryption memory means, said decryption memory means including an address input for receiving said encrypted digital signal samples for addressing said digital signal samples and a data port for providing said digital signal samples responsive to said encrypted digital signal samples; and encryption programming means for providing said encryption memory means with said encrypted digital signal samples, said encryption programming means including addressing means for storing said encrypted digital signal samples at said predetermined ones of said storage locations.

Claim 13

A communication system for transmitting and receiving encrypted digital signal samples, said system comprising: generating means for generating digital signal samples to be encrypted; encryption memory means including a first plurality of addressable storage locations for storing said encrypted digital signal samples at predetermined ones of said storage locations, said memory means including an address input for receiving said digital signal samples for addressing said encrypted digital signal samples and a data port for providing said encrypted digital signal samples responsive to said digital signal samples; transmitting means for transmitting said encrypted digital signal samples; receiving means for receiving said encrypted digital signal samples; decryption memory means including a second plurality of addressable storage locations for storing said digital signal samples at storage locations complimentary to said encrypted digital signal sample storage locations of said encryption memory means, said decryption memory means including an address input for receiving said encrypted digital signal samples for addressing said digital signal samples and a data port for providing said digital signal samples responsive to said encrypted digital signal samples; and encryption programming means for providing said encryption memory means with said encrypted digital signal samples, said encryption programming means including addressing means for storing said encrypted digital signal samples at said predetermined ones of said storage locations.

Claim 14

A system as defined in claim 11 wherein said encryption programming means comprises a microprocessor having an address output for providing memory means addresses for addressing said storage locations of said encryption memory means and a data output coupled to said encryption memory means data port for providing said memory means with said encrypted digital signal samples.

Claim 15

A system as defined in claim 12 further including a first multiplexer for providing said encryption memory mean address input with either said digital signal samples to be encrypted or said memory means addresses from said microprocessor and a second multiplexer for providing said encrypted digital signal samples from said encryption memory means data port or for providing said encryption memory means data port with said encrypted digital signal samples from said microprocessor.

Claim 16

A system as defined in claim 11 further including decryption programming means for providing said decryption memory means with said digital signal samples, said decryption programming means including addressing means for storing said digital signal samples at said storage locations complimentary to said encrypted digital signal sample storage locations of said encryption memory means.

Claim 17

A system as defined in claim 14 wherein said decryption programming means comprises a microprocessor having an address output for providing memory means addresses for addressing said storage locations of said decryption memory means and a data output coupled to said decryption memory means data port for providing said decryption memory means with said digital signal samples.

Claim 18

A system as defined in claim 15 further including a first multiplexer for providing said decryption memory means address input with either said encrypted digital signal samples or said memory means addresses from said microprocessor and a second multiplexer for providing said digital signal samples from said decryption memory means data port or for providing said decryption memory means data port with said digital signal samples from said microprocessor.

Claim 19

A system as defined in claim 11 wherein said encryption memory means comprises a random access memory.

Claim 20

A system as defined in claim 11 wherein said encryption memory means comprises a reprogrammable non-volatile memory.

Claim 21

A system as defined in claim 11 further including encoder means coupled to said encryption memory means address input for providing said encryption memory means with said digital signal samples to be encrypted.

Claim 22

A system as defined in claim 19 wherein said encoder means comprises a pulse code modulation encoder.

Claim 23

A system as defined in claim 19 wherein said decoder means comprises an adaptive pulse code modulation decoder.

Claim 24

A system as defined in claim 11 further including encoder means coupled to said encryption memory means data port for encoding said encrypted digital signal samples.

Claim 25

A system as defined in claim 22 wherein said decoder means comprises a pulse code modulation decoder.

Claim 26

A system as defined in claim 22 wherein said decoder means comprises an adaptive pulse code modulation decoder.

Claim 27

A system as defined in claim 11 wherein said decryption memory means comprises a random access memory.

Claim 28

A system as defined in claim 11 wherein said decryption memory means comprises a reprogammable non-volatile memory.

Claim 29

A system as defined in claim 11 further including decoder means coupled to said decryption memory means data port for decoding said digital signal samples.

Claim 30

A system as defined in claim 27 wherein said decoder means comprises a pulse code modulation decoder.

Claim 31

A system as defined in claim 27 wherein said decoder means comprises an adaptive pulse code modulation decoder.

Claim 32

A system as defined in claim 11 further including decoding means coupled to said decryption memory means address input for providing said decryption memory means with said encrypted digital signal samples.

Claim 33

A system as defined in claim 30 wherein said decoder means comprises a pulse code modulation decoder.

Claim 34

A system as defined in claim 30 wherein said decoder means comprises an adaptive pulse code modulation decoder.