Abstract A circuit arrangement for establishing conference connections comprising conference units is described, which units are linked to form a loop (L). In this loop (L) sum codewords consisting of sample values of the signals of all participants in a conference are transmitted from one conference unit to the next. In each conference unit a sum codeword is updated so that the sample value of a conference signal from the previous loop travel is replaced by the current sample value. In order to enable the monotoring of a travel of sum codewords through the loop with a circuit arrangement of this type and in order to have the sum codewords pass through the loop in a predetermined brief period of time without a necessity for a synchronization of individual processing modules of the conference units, the function of one or more conference units is taken over by a programmed processor (P1 to P4). The exchange of data between the conferees and the processors is controlled by means of an interface circuit (PO). In addition to the sum codewords also test words consisting of transformed sum codewords pass through the loop (L). Sum codewords and test words are buffered in input memories (ES1 to ES4) during their travel through the loop until the associated processor (P1 to P4) has finished the program modules for which the sum codeword or test word respectively is used. These modules are programmed in the individual processors (P1 to P4) in a time offset order.
Circuit arrangement for establishing conference connections among a plurality of participant conference units linked to form a loop, comprising; means responsive to sample values of signals of all the participant conference units in a conference for forming a sum codeword; means for passing the sum codeword from one conference unit of the loop to the next; updating means in each participant conference unit for updating the sum codeword by the use of the actual sample value and forming a conference signal from the sum codeword; a programmed processor for taking over the function of one or more participant conference units; interface circuit means coupled to the programmed processor for generating write and read commands by which the programmed processor is actuated for controlling the conference signal input and output; means in each processor for writing each updated sum codeword into an input memory of the next processor; means for transforming each updated sum codeword into a test word and overwriting the contents of the input memory of the next processor with the test word at a later instant, means in the next processor in the loop for reading the test word from this memory, comparing the sum codeword previously contained in this memory to the testword and produces an alarm signal depending upon the result of the comparison; sequencing means for causing successive processors to perform the program items of updating the sum codeword and comparing the sum codeword to the test word in a time offset order.
Claim 2
Dependent Claim
248 words
Circuit arrangement for establishing conference connections among a plurality of participant conference units linked to form a loop, comprising; means responsive to sample values of signals of all the participant conference units in a conference for forming a sum codeword; means for passing the sum codeword from one conference unit of the loop to the next; updating means in each participant conference unit for updating the sum codeword by the use of the actual sample value and forming a conference signal from the sum codeword; a programmed processor for taking over the function of one or more participant conference units; interface circuit means coupled to the programmed processor for generating write and read commands by which the programmed processor is actuated for controlling the conference signal input and output; means in each processor for writing each updated sum codeword into an input memory of the next processor; means for transforming each updated sum codeword into a test word and overwriting the contents of the input memory of the next processor with the test word at a later instant, means in the next processor in the loop for reading the test word from this memory, comparing the sum codeword previously contained in this memory to the testword and produces an alarm signal depending upon the result of the comparison; sequencing means for causing successive processors to perform the program items of updating the sum codeword and comparing the sum codeword to the test word in a time offset order.
Claim 3
Dependent Claim
25 words
Circuit arrangement as claimed in claim 1, in which the input memories comprise serial-to-parallel converters and the output memories comprise parallel-to-serial converters (AS1 to AS4).
Claim 4
Dependent Claim
20 words
Circuit arrangement as claimed in claim 2, in which the processors, the input, and the output converters comprise integrated components.
Claim 5
Dependent Claim
19 words
Circuit arrangement as claimed in claim 1, characterised in that sum codewords inverted bit-by-bit are used as test words.
Claim 6
Dependent Claim
15 words
The circuit of claim 2, wherein sum codewords inverted bit-by-bit are used as test words.
Claim 7
Dependent Claim
15 words
The circuit of claim 3, wherein sum codewords inverted bit-by-bit are used as test words.