US5199000A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory circuit having switched voltage supply for data bus lines
Assignee: NEC Corp
•
Filing: 1991-03-27
•
Granted: 1993-03-30
•
Expires: 2011-03-27
Abstract
Abstract A semiconductor memory circuit comprises a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines. The pair of digit lines are pulled up through a pair of load transistors, respectively, and connected through a pair of gate transistors to a corresponding pair of data bus lines, respectively, which are in turn connected to a sense amplifier and pulled down through a pair of driving transistors, respectively. A voltage supply circuit is provided which includes a voltage divider circuit composed of series-connected dummy transistors having the same characteristics as those of the load, gate and driving transistors which cooperate to determine a potential on the pair of data bus lines when the pair of digit lines and the pair of data bus lines are selected. On the basis of a reference voltage generated by the voltage divider circuit, the voltage supply circuit operates to generate a voltage to be supplied to the pair of data bus lines when the pair of digit lines and the pair of data bus lines are not selected. The voltage generated by the voltage supply circuit is supplied to the pair of digit lines or the pair of data bus lines through a switch circuit which is turned on when the pair of digit lines and the pair of data bus lines are not selected.
Inventors
- 👤 Hiroyuki Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 01:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1048; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
215 words
A semiconductor memory circuit comprising a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines, said pair of digit lines being connected through a switch circuit to a corresponding pair of data bus lines, which are in turn connected to a sense amplifier, the semiconductor memory circuit also including a voltage supply circuit composed of circuit elements having the same characteristics as that of circuit elements included in a circuit for determining a potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, said voltage supply circuit operating to generate, on the basis of the potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, a voltage to be applied to said pair of data bus lines when said pair of digit lines and said pair of data bus lines are not selected, the voltage generated by said voltage supply circuit being supplied to said pair of digit lines or said pair of data bus lines through another switch circuit which is turned on when said pair of digit lines and said pair of data bus lines are not selected.
Claim 2
Dependent Claim
215 words
A semiconductor memory circuit comprising a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines, said pair of digit lines being connected through a switch circuit to a corresponding pair of data bus lines, which are in turn connected to a sense amplifier, the semiconductor memory circuit also including a voltage supply circuit composed of circuit elements having the same characteristics as that of circuit elements included in a circuit for determining a potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, said voltage supply circuit operating to generate, on the basis of the potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, a voltage to be applied to said pair of data bus lines when said pair of digit lines and said pair of data bus lines are not selected, the voltage generated by said voltage supply circuit being supplied to said pair of digit lines or said pair of data bus lines through another switch circuit which is turned on when said pair of digit lines and said pair of data bus lines are not selected.
Claim 3
Dependent Claim
233 words
A semiconductor memory circuit comprising a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines, said pair of digit lines being pulled up through a pair of load transistors, respectively, and connected through a pair of gate transistors to a corresponding pair of data bus lines, respectively, which are in turn connected to a sense amplifier and pulled down through a pair of driving transistors, respectively, the semiconductor memory circuit also including a voltage supply circuit which includes a voltage divider circuit composed of series-connected dummy transistors having the same characteristics as those of said load, gate and driving transistors which cooperate to determine a potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, said voltage supply circuit operating to generate, on the basis of a reference voltage generated by said voltage divider circuit, a voltage to be supplied to said pair of data bus lines when said pair of digit lines and said pair of data bus lines are not selected, the voltage generated by said voltage supply circuit is supplied to said pair of digit lines or said pair of data bus lines through a first switch circuit which is turned on when said pair of digit lines and said pair of data bus lines are not selected.
Claim 4
Dependent Claim
233 words
A semiconductor memory circuit comprising a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines, said pair of digit lines being pulled up through a pair of load transistors, respectively, and connected through a pair of gate transistors to a corresponding pair of data bus lines, respectively, which are in turn connected to a sense amplifier and pulled down through a pair of driving transistors, respectively, the semiconductor memory circuit also including a voltage supply circuit which includes a voltage divider circuit composed of series-connected dummy transistors having the same characteristics as those of said load, gate and driving transistors which cooperate to determine a potential on said pair of data bus lines when said pair of digit lines and said pair of data bus lines are selected, said voltage supply circuit operating to generate, on the basis of a reference voltage generated by said voltage divider circuit, a voltage to be supplied to said pair of data bus lines when said pair of digit lines and said pair of data bus lines are not selected, the voltage generated by said voltage supply circuit is supplied to said pair of digit lines or said pair of data bus lines through a first switch circuit which is turned on when said pair of digit lines and said pair of data bus lines are not selected.
Claim 5
Dependent Claim
148 words
A semiconductor memory circuit claimed in claim 2 wherein said gate transistors have commonly connected gates receiving a digit line selection signal, so that said gate transistors are turned on when said pair of digit lines are selected, and said driving transistors have commonly connected gates receiving a data bus selection signal, so that said driving transistors are turned on when said pair of data bus lines are selected, and wherein said switch circuit includes a pair of transfer gate transistors connected between an output of said voltage supply circuit and said pair of data bus lines, respectively, gates of transfer gate transistors being connected in common to receive said data bus selection signal so that when said driving transistors are turned off, said transfer gate transistors are turned on whereby the voltage generated by said voltage supply circuit is supplied to said pair of data bus lines.
Claim 6
Dependent Claim
119 words
A semiconductor memory circuit claimed in claim 3 wherein said voltage supply circuit includes a first bipolar transistor in the form of an emitter follower having a collector connected to a high voltage supply voltage and a base connected to receive said reference voltage generated by said voltage divider circuit, a voltage shift circuit having a resistor and at least one diode connected in series between said high voltage supply voltage and said emitter of said first bipolar transistor, and a second bipolar transistor in the form of an emitter follower having a base connected to a connection node between said resistor and said at least one diode and an emitter giving said output of said voltage supply circuit.
Claim 7
Dependent Claim
63 words
A semiconductor memory circuit claimed in claim 3 wherein said pair of data bus lines are connected through a second switch circuit to a pair of common data bus lines which are in turn connected to said sense amplifier and wherein the voltage generated by said voltage supply circuit is supplied to said pair of data bus lines through said first switch circuit.
Claim 8
Dependent Claim
63 words
A semiconductor memory circuit claimed in claim 5 wherein said voltage supply circuit includes a bipolar transistor in the form of an emitter follower having a collector connected to a high voltage supply voltage and a base connected to receive said reference voltage generated by said voltage divider circuit, an emitter of said bipolar transistor giving said output of said voltage supply circuit.
References Cited (Backward Citations)
US5050127A
Cited
US5010521A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-29 | 1996-09-28 | 1997-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-29 | 2000-09-28 | 2001-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-29 | 2004-09-28 | 2005-03-30 | $7700.00 | Window Closed / Lapsed |