Reactive volt-ampere-hour meter

Claim 2

A reactive volt-ampere-hour meter comprising: a 90-degrees phase shift circuit for receiving a first and a second electric signal representative of, respectively, an AC voltage and an AC current fed to a load and generating a pair of electric signals by shifting the phase of either of said first and second electric signals by 90 degrees; a multiplier for multiplying said pair of electric signals to thereby produce a third electric signal representative of a product of said pair of electric signals; a cumulative adder for cumulatively adding the third electric signals and generating a first carry pulse when the cumulative sum reaches a predetermined upper limit or generating a borrow pulse when said cumulative sum reaches a predetermined lower limit; a first up-down counter for up-counting the first carry pulses and down-counting the borrow pulses to generate a second carry pulse when the count of said first up-down counter reaches a predetermined value; a second up-down counter for up-counting said borrow pulses and down-counting said first carry pulses to generate a third carry pulse when the count of said second up-down counter reaches a predetermined value; an up-counter for up-counting said second and third carry pulses; and a display for displaying the count of said up-counter.

Claim 3

A meter as claimed in claim 1, wherein said cumulative adder comprises: a first integrating unit for cumulatively adding the third electric signals only when said third electric signals have positive values and generating said first carry pulse when the cumulative sum reaches said upper limit; and a second integrating unit for cumulatively adding said third electric signals only when said third electric signals have negative values and generating said borrow pulse when the cumulative sum reaches said predetermined lower limit.

Claim 4

A meter as claimed in claim 1, wherein said first and second up-down counters each comprises: input terminals for receiving preset data; a preset enable input terminal for receiving a command for forcibly setting the count to said preset data; and a connection line for delivering said second or third carry pulse generated by said up-down counter itself to said preset enable input terminal.

Claim 5

A meter as claimed in claim 1, wherein said first and second electric signals comprise analog signals, said meter further comprising between said 90-degrees phase shift circuit and said multiplier a first and a second filter for substantially removing needless frequency components from said pair of electric signals output by said 90-degrees phase shift circuit, and a first and a second analog-to-digital (A/D) converter for converting respectively output signals of said first and second filters to digital signals and feeding said digital signals to said multiplier.

Claim 6

A meter as claimed in claim 1, further comprising at a stage preceding said 90-degrees phase shift circuit a first and a second filter for substantially removing needless components from said two electric signals representative of the AC voltage and said AC current fed to the load, and a first and a second A/D converter for converting respectively the output signals of said first and second filters to digital signals and delivering said digital signals to said 90-degrees phase shift circuit as said first and second electric signals.

Claim 7

A meter as claimed in claim 5, wherein said 90-degrees phase shift circuit comprises: a phase shift circuit comprising a period detector for detecting the period of one of said two electric signals, a frequency divider for dividing a timing clock of said digital signals to thereby generate frequency divided output pulses, a counter for counting said frequency divided output pulses and resetting the count in response to an output signal of said period detector to thereby generate a first address signal representative of the number of pulses of said timing clock which are included in one-fourth of the period of said one electric signal, a coincidence circuit for comparing a second address signal representative of an address to access and said first address signal and, when said first and second address signals coincide, generating a coincidence pulse, an address generator for counting the pulses of said timing clock and resetting the count in response to said coincidence pulse to thereby generate a signal representative of said count as said second address signal, and a buffer memory for receiving one of said first and second electric signals to read, during the former half of an access period to an address indicated by said second address signal, the content of said address and write the received electric signal during the latter half of said access period; and a connection line for directly conducting the other one of said first and second electric signals.