US5197028A — Semiconductor memory device with dual reference e…

Claim 1

Independent Claim 454 words

A semiconductor memory device comprising: a memory cell having a drain, a gate and a source, said source of said memory cell being connected to a ground line, said gate of said memory cell being supplied with a predetermined potential for reading memory cell data; a bit line connected to said drain of said memory cell for receiving said memory cell data; a bit line potential setting means connected between said bit line and a memory cell data detecting terminal for setting a potential value of said bit line lower than that of a power source line; a load transistor connected between said memory cell data detecting terminal and said power source line; a first reference cell having a drain, a gate and a source, said gate of said first reference cell having applied thereto said predetermined potential, said source of said first reference cell being connected to said ground line; a first reference line connected to said drain of said first reference cell for receiving first reference cell data; first reference line potential setting means connected between said first reference line and a first reference cell data detecting terminal for setting a potential value of said first reference line lower than that of said power source line; a first reference load transistor connected between said first reference cell data detecting terminal and said power source line, said first reference load transistor having a lower conductance value than that of said load transistor; a second reference cell having a drain, a gate and a source, said source of said second reference cell being connected to said ground line; a second reference line connected to said drain of said second reference cell for receiving second reference cell data; second reference line potential setting means connected between said second reference line and a second reference cell data detecting terminal for setting a potential value of said second reference line lower than that of said power source line; a second reference load transistor connected between said second reference data detecting terminal and said power source line, said second reference load transistor having a conductance value equal to that of said load transistor; gate potential generating means having an output terminal connected to said gate of said second reference cell for controlling a gate potential of said second reference cell, so as to make a potential value at said first reference cell data detecting terminal equal to the potential value at said second reference cell data detecting terminal; and data detecting means for reading out said memory cell data in accordance with a comparison result between a potential value at said memory cell data detecting terminal and said potential value at said second reference cell data detecting terminal.

Claim 2

Dependent Claim 454 words

A semiconductor memory device comprising: a memory cell having a drain, a gate and a source, said source of said memory cell being connected to a ground line, said gate of said memory cell being supplied with a predetermined potential for reading memory cell data; a bit line connected to said drain of said memory cell for receiving said memory cell data; a bit line potential setting means connected between said bit line and a memory cell data detecting terminal for setting a potential value of said bit line lower than that of a power source line; a load transistor connected between said memory cell data detecting terminal and said power source line; a first reference cell having a drain, a gate and a source, said gate of said first reference cell having applied thereto said predetermined potential, said source of said first reference cell being connected to said ground line; a first reference line connected to said drain of said first reference cell for receiving first reference cell data; first reference line potential setting means connected between said first reference line and a first reference cell data detecting terminal for setting a potential value of said first reference line lower than that of said power source line; a first reference load transistor connected between said first reference cell data detecting terminal and said power source line, said first reference load transistor having a lower conductance value than that of said load transistor; a second reference cell having a drain, a gate and a source, said source of said second reference cell being connected to said ground line; a second reference line connected to said drain of said second reference cell for receiving second reference cell data; second reference line potential setting means connected between said second reference line and a second reference cell data detecting terminal for setting a potential value of said second reference line lower than that of said power source line; a second reference load transistor connected between said second reference data detecting terminal and said power source line, said second reference load transistor having a conductance value equal to that of said load transistor; gate potential generating means having an output terminal connected to said gate of said second reference cell for controlling a gate potential of said second reference cell, so as to make a potential value at said first reference cell data detecting terminal equal to the potential value at said second reference cell data detecting terminal; and data detecting means for reading out said memory cell data in accordance with a comparison result between a potential value at said memory cell data detecting terminal and said potential value at said second reference cell data detecting terminal.

Claim 3

Dependent Claim 27 words

A semiconductor memory device according to claim 1, wherein said second reference line potential setting means is a duplicate circuit of said bit line potential setting means.

Claim 4

Dependent Claim 32 words

A semiconductor memory device according to claim 1, wherein a delay means is provided between said output terminal of said gate potential generating means and said gate of said second reference cell.

Claim 5

Dependent Claim 376 words

A semiconductor memory device comprising: a memory cell having a drain, a gate and a source, said source of said memory cell being connected to a ground line, said gate of said memory cell having applied thereto a predetermined potential for reading out a memory cell data; a bit line connected to said drain of said memory cell for receiving said memory cell data; a bit line potential setting means connected between said bit line and a memory cell data detecting terminal for setting a potential value of said bit line lower than that of a power source line; a load transistor connected between said memory cell data detecting terminal and said power source line; a reference cell having a drain, a gate and a source, said source of said reference cell being connected to said ground line; a reference line connected to said drain of said first reference cell for receiving reference cell data; reference line potential setting means connected between said reference line and a reference cell data detecting terminal for setting a potential value of said reference line lower than that of said power source line; a reference load transistor connected between said reference cell data detecting terminal and said power source line, said reference load transistor having a conductance value which is equal to that of said load transistor; potential generating means for generating a comparison potential having a value which is lower than a potential value at said memory cell data detecting terminal when said memory cell is in a nonconductive state, and which is higher than a potential value at said memory cell data detecting terminal when said memory cell is in a conductive state; potential comparing means having an output terminal connected to said gate of said reference cell for controlling a current flowing through said reference cell so as o make a potential value at said reference cell data detecting terminal equal to said comparison potential value; a delay means connected between said output terminal of said potential comparing means and said gate of said reference cell; and data detecting means for comparing a potential at said memory cell data detecting terminal with a potential at said reference cell data detecting terminal to detect said memory cell data.

Claim 6

Dependent Claim 376 words

A semiconductor memory device comprising: a memory cell having a drain, a gate and a source, said source of said memory cell being connected to a ground line, said gate of said memory cell having applied thereto a predetermined potential for reading out a memory cell data; a bit line connected to said drain of said memory cell for receiving said memory cell data; a bit line potential setting means connected between said bit line and a memory cell data detecting terminal for setting a potential value of said bit line lower than that of a power source line; a load transistor connected between said memory cell data detecting terminal and said power source line; a reference cell having a drain, a gate and a source, said source of said reference cell being connected to said ground line; a reference line connected to said drain of said first reference cell for receiving reference cell data; reference line potential setting means connected between said reference line and a reference cell data detecting terminal for setting a potential value of said reference line lower than that of said power source line; a reference load transistor connected between said reference cell data detecting terminal and said power source line, said reference load transistor having a conductance value which is equal to that of said load transistor; potential generating means for generating a comparison potential having a value which is lower than a potential value at said memory cell data detecting terminal when said memory cell is in a nonconductive state, and which is higher than a potential value at said memory cell data detecting terminal when said memory cell is in a conductive state; potential comparing means having an output terminal connected to said gate of said reference cell for controlling a current flowing through said reference cell so as o make a potential value at said reference cell data detecting terminal equal to said comparison potential value; a delay means connected between said output terminal of said potential comparing means and said gate of said reference cell; and data detecting means for comparing a potential at said memory cell data detecting terminal with a potential at said reference cell data detecting terminal to detect said memory cell data.

Claim 7

Dependent Claim 360 words

A semiconductor memory device comprising: a memory cell array having a plurality of memory cell transistors disposed in a matrix; word lines for selectively applying a predetermined potential to the gates of selected memory cell transistors in said memory cell array; a bit line connected to said drains of said memory cell transistors for receiving selected memory cell data; bit line potential setting means connected between said bit line and a memory cell data detecting terminal for setting a potential value of said bit line lower than that of a power source line; a load transistor connected between said memory cell data detecting terminal and said power source line; a reference cell having a drain, a gate and a source said source of said reference cell being connected to a ground line; a reference line connected to said drain of said first reference cell for receiving reference cell data; a reference line potential setting means connected between said reference line and a reference cell data detecting terminal for setting a potential value of said reference line lower than that of said power source line; a reference load transistor connected between said reference cell data detecting terminal and said power source line, said reference load transistor having a conductance value equal tot hat of said load transistor; potential generating means for generating a comparison potential having a value low than a potential value at said memory cell data detecting terminal when said memory cell is in a nonconductive state, ad which is higher than a potential value at said memory cell data detecting terminal when said memory cell is a conductive state; potential comparing means, having an output terminal connected to said gate of said reference cell, for controlling the current flowing through said reference cell, so as to make a potential value at said reference cell data detecting terminal equal to said comparison potential value; a delay means connected between said output terminal and said gate of said reference cell; and data detecting means for comparing a potential at said memory cell data detecting terminal with a potential at reference cell data detecting terminal to detect said memory cell data.

Claim 8

Dependent Claim 360 words

A semiconductor memory device comprising: a memory cell array having a plurality of memory cell transistors disposed in a matrix; word lines for selectively applying a predetermined potential to the gates of selected memory cell transistors in said memory cell array; a bit line connected to said drains of said memory cell transistors for receiving selected memory cell data; bit line potential setting means connected between said bit line and a memory cell data detecting terminal for setting a potential value of said bit line lower than that of a power source line; a load transistor connected between said memory cell data detecting terminal and said power source line; a reference cell having a drain, a gate and a source said source of said reference cell being connected to a ground line; a reference line connected to said drain of said first reference cell for receiving reference cell data; a reference line potential setting means connected between said reference line and a reference cell data detecting terminal for setting a potential value of said reference line lower than that of said power source line; a reference load transistor connected between said reference cell data detecting terminal and said power source line, said reference load transistor having a conductance value equal tot hat of said load transistor; potential generating means for generating a comparison potential having a value low than a potential value at said memory cell data detecting terminal when said memory cell is in a nonconductive state, ad which is higher than a potential value at said memory cell data detecting terminal when said memory cell is a conductive state; potential comparing means, having an output terminal connected to said gate of said reference cell, for controlling the current flowing through said reference cell, so as to make a potential value at said reference cell data detecting terminal equal to said comparison potential value; a delay means connected between said output terminal and said gate of said reference cell; and data detecting means for comparing a potential at said memory cell data detecting terminal with a potential at reference cell data detecting terminal to detect said memory cell data.

Claim 9

Dependent Claim 34 words

A semiconductor memory device according to claim 5, wherein the delay mean is formed by a dummy work line connected to the gates of the dummy cell transistors disposed within said memory cell array.

Claim 10

Dependent Claim 121 words

A semiconductor memory device according to claim 6, wherein said potential generating means comprises: a dummy cell having a drain, a gate and a source, said source of said dummy cell being connected to said ground line, said gate of said dummy cell having applied thereto said predetermined potential; drain potential setting means connected between said drain of said dummy cell and a comparison potential outputting terminal, for setting a potential value of said drain of said dummy cell lower than that of said power source line; and a dummy cell load transistor connected between said comparison potential outputting terminal and said power source line, said dummy cell load transistor having a conductance value equal to that of said load transistor.

Claim 11

Dependent Claim 19 words

A semiconductor memory device according to claim 7, wherein said dummy cell is selected by a selected word line.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-03-22	1996-09-21	1997-03-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-03-22	2000-09-21	2001-03-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-03-22	2004-09-21	2005-03-23	$7700.00	Window Closed / Lapsed

Semiconductor memory device with dual reference elements

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