US5195010A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrostatic discharge voltage protection circuit for a solid state instrument
Assignee: Vantiva SA
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Filing: 1990-01-23
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Granted: 1993-03-16
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Expires: 2010-01-23
Abstract
Abstract A protection circuit for a solid state instrument includes a plurality of fuses and a switching device arranged in parallel with the input capacitance of the solid state instrument, The fuses protect the instrument from high voltage surges, and the switching device protects the instrument from lower voltage surges. The fuses and the switching device are solid state devices and thus can be fabricated along with the solid state instrument.
Inventors
- 👤 Joseph Dresner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:02
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H02; H02H; H02H9/00; H02H9/04; H02H9/045; H02H9/046
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
134 words
A protection circuit having an input line and a ground line for protecting a solid state instrument from electrostatic discharges comprising: a plurality of solid state fusing devices arranged in parallel between said input line and said ground line, the input capacitance of said solid state instrument also being arranged between said input line and said ground line, said fusing devices protecting said instrument from electrostatic discharges above a minimum voltage; a solid state switching device arranged in parallel with said input capacitance for shunting currents produced by electrostatic discharges below said minimum voltage; and a resistor in combination with said input capacitance, said resistor having a value whereby the RC time constant of said resistor and said input capacitance is higher than the switching time of said fusing devices and said switching device.
Claim 2
Dependent Claim
134 words
A protection circuit having an input line and a ground line for protecting a solid state instrument from electrostatic discharges comprising: a plurality of solid state fusing devices arranged in parallel between said input line and said ground line, the input capacitance of said solid state instrument also being arranged between said input line and said ground line, said fusing devices protecting said instrument from electrostatic discharges above a minimum voltage; a solid state switching device arranged in parallel with said input capacitance for shunting currents produced by electrostatic discharges below said minimum voltage; and a resistor in combination with said input capacitance, said resistor having a value whereby the RC time constant of said resistor and said input capacitance is higher than the switching time of said fusing devices and said switching device.
Claim 3
Dependent Claim
14 words
The protection circuit of claim 1 wherein said fusing devices are amorphous silicon devices.
Claim 4
Dependent Claim
19 words
The protection circuit of claim 2 wherein said solid state switching device is an amorphous silicon thin film transistor.
Claim 5
Dependent Claim
15 words
The protection circuit of claim 3 wherein said thin film transistor has a floating gate.
Claim 6
Dependent Claim
17 words
The protection circuit of claim 4 wherein said solid state instrument is a liquid crystal display device.
Claim 7
Dependent Claim
31 words
The protection circuit of claim 1 wherein said solid state fusing devices are arranged in a single solid state strip, and wherein said solid state fusing devices are amorphous silicon devices.
Claim 8
Dependent Claim
19 words
The protection circuit of claim 6 wherein said solid state switching device is an amorphous silicon thin film transistor.
Claim 9
Dependent Claim
17 words
The protection circuit of claim 7 wherein said solid state instrument is a liquid crystal display device.
Claim 10
Dependent Claim
114 words
A protection circuit including a plurality of parallel fusing devices each of said fuzes comprising: an insulative substrate; a first layer of Si 3 N 4 overlying one surface of said substrate; a second layer of undoped semiconductor material overlying said first layer; a third layer of doped semiconductor material overlying said second layer; a conductive electrode overlying said third layer; a channel, having a dimension L, extending through said conductive electrode and said third layer and extending partially through said second layer, whereby the bottom of said channel lies within the distance d of said first layer; and a fourth layer of Si 3 N 4 overlying said third layer and said channel.
Claim 11
Dependent Claim
114 words
A protection circuit including a plurality of parallel fusing devices each of said fuzes comprising: an insulative substrate; a first layer of Si 3 N 4 overlying one surface of said substrate; a second layer of undoped semiconductor material overlying said first layer; a third layer of doped semiconductor material overlying said second layer; a conductive electrode overlying said third layer; a channel, having a dimension L, extending through said conductive electrode and said third layer and extending partially through said second layer, whereby the bottom of said channel lies within the distance d of said first layer; and a fourth layer of Si 3 N 4 overlying said third layer and said channel.
Claim 12
Dependent Claim
39 words
The protection circuit of claim 9 wherein said fusing devices are arranged in a single solid state strip, and wherein said dimension L is selected such that said fusing devices are protection against electrostatic discharges above a minimum voltage.
Claim 13
Dependent Claim
20 words
The protection circuit of claim 10 wherein said thin film transistor is protection against electrostatic discharges below said minimum voltage.
Claim 14
Dependent Claim
13 words
The protection circuit of claim 11 wherein said semiconductor material is amorphous silicon.
Claim 15
Dependent Claim
13 words
The protection circuit of claim 9 wherein said semiconductor material is amorphous silicon.
Claim 16
Dependent Claim
105 words
A solid state fusing device comprising: an insulative substrate; a first layer of Si 3 N 4 overlying one surface of said substrate; a second layer of undoped semiconductor material overlying said first layer; a third layer of doped semiconductor material overlying said second layer; a conductive electrode overlying said third layer; a channel, having a dimension L, extending through said conductive electrode and said third layer and extending partially through said second layer, whereby the bottom of said channel lies within the distance d of said first layer; and a fourth layer of Si 3 N 4 overlying said third layer and said channel.
Claim 17
Dependent Claim
105 words
A solid state fusing device comprising: an insulative substrate; a first layer of Si 3 N 4 overlying one surface of said substrate; a second layer of undoped semiconductor material overlying said first layer; a third layer of doped semiconductor material overlying said second layer; a conductive electrode overlying said third layer; a channel, having a dimension L, extending through said conductive electrode and said third layer and extending partially through said second layer, whereby the bottom of said channel lies within the distance d of said first layer; and a fourth layer of Si 3 N 4 overlying said third layer and said channel.
Claim 18
Dependent Claim
25 words
The device of claim 14 wherein said dimension L is selected such that said fusing devices are protection against electrostatic discharges above a minimum voltage.
Claim 19
Dependent Claim
15 words
The solid state fusing device of claim 14 wherein said semiconductor material is amorphous silicon.
References Cited (Backward Citations)
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| 7.5 Years (Year 8) | 2000-03-15 | 2000-09-14 | 2001-03-16 | $3760.00 | Window Closed / Lapsed |
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