US5193221A
Expired / Lapsed
US
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Signal output apparatus
Assignee: Toshiba Corp
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Filing: 1990-09-12
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Granted: 1993-03-09
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Expires: 2010-09-12
Abstract
Abstract A signal output apparatus particularly suitable for wireless remote control unit is disclosed. This signal output apparatus includes a CPU section; an output data storage section for storing an output data given by the CPU section; a main clock signal generator section; a count section for generating a timing signal for representing the output data in accordance with the main clock signal generated by the main clock signal generator; an output control section for generating an output control signal whose level changes with the contents of the output data, in response to the timing signal; and a signal output section for receiving the main clock signal and the output control signal for outputting the main clock signal intermittent in response to the level change of the output control signal. The main clocks are modulated by the output control section and signal output section of the signal output apparatus.
Inventors
- 👤 Kazuteru Saginao
- 👤 Hideyuki Okanuma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:47
CPC Classifications
G; G11; G11B; G11B27/00; G11B27/10; H; H03; H03J; H03J1/00; H03J1/0008; H03J1/0025; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/20; H04B1/202
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
218 words
A signal output apparatus comprising: a CPU section; output data storage means for storing output data from said CPU section; main clock signal generating means outputting a main clock signal; a count circuit receiving said main clock signal and outputting a timing signal equal to a predetermined number of said main clock signals; output control means for generating an output control signal comprised of "0" data and "1" data according to said output data, said "0" data and "1" data being expressed by different combinations of high level period and low level period, in response to said timing signal, wherein said output control means includes: an address selection circuit for decoding an address signal output by said CPU section and selecting an address of said output data storage unit, a parallel-to-serial circuit for time sequentially outputting the data in said output data storage unit at an address selected by said address selection circuit, and a one-data variable counter receiving a logical AND between an output from said count unit and an output from said parallel-to-serial circuit at said selected address and outputting said output control signal; and signal output means, receiving said main clock signal and said output control signal, for outputting said main clock signal intermittently in response to a level change of said output control signal.
Claim 2
Dependent Claim
218 words
A signal output apparatus comprising: a CPU section; output data storage means for storing output data from said CPU section; main clock signal generating means outputting a main clock signal; a count circuit receiving said main clock signal and outputting a timing signal equal to a predetermined number of said main clock signals; output control means for generating an output control signal comprised of "0" data and "1" data according to said output data, said "0" data and "1" data being expressed by different combinations of high level period and low level period, in response to said timing signal, wherein said output control means includes: an address selection circuit for decoding an address signal output by said CPU section and selecting an address of said output data storage unit, a parallel-to-serial circuit for time sequentially outputting the data in said output data storage unit at an address selected by said address selection circuit, and a one-data variable counter receiving a logical AND between an output from said count unit and an output from said parallel-to-serial circuit at said selected address and outputting said output control signal; and signal output means, receiving said main clock signal and said output control signal, for outputting said main clock signal intermittently in response to a level change of said output control signal.
Claim 3
Dependent Claim
21 words
A signal output apparatus according to claim 1, wherein said main clock signal generating means is included in said CPU section.
Claim 4
Dependent Claim
26 words
A signal output apparatus according to claim 1, wherein said count means includes means for generating a signal obtained from said main clock signal through frequency-division.
Claim 5
Dependent Claim
33 words
A signal output apparatus according to claim 3, wherein said signal output unit is a logical AND means for obtaining a logical AND between said main clock signal and said output control signal.
Claim 6
Dependent Claim
233 words
A remote control commander comprising: a CPU section; output data storage means for storing output data from said CPU section; main clock signal generating means outputting a main clock signal; a count circuit receiving said main clock signal and outputting a timing signal equal to a predetermined number of said main clock signals; output control means for generating an output control signal comprised of "0" data and "1" data according to said output data, said "0" data and "1" data being expressed by different combinations of high level period and low level period, in response to said timing signal, wherein said output control means includes: an address selection circuit for decoding an address signal output by said CPU section and selecting an address of said output data storage unit, a parallel-to-serial circuit for time sequentially outputting the data in said output data storage unit at an address selected by said address selection circuit, and a one-data variable counter receiving a logical AND between an output from said count unit and an output from said parallel-to-serial circuit at said selected address and outputting said output control signal; signal output means, receiving said main clock signal and said output control signal, for outputting said main clock signal intermittently in response to a level change of said output control signal; and conversion means for receiving said intermittent main clock signal and generating a remote control signal.
Claim 7
Dependent Claim
233 words
A remote control commander comprising: a CPU section; output data storage means for storing output data from said CPU section; main clock signal generating means outputting a main clock signal; a count circuit receiving said main clock signal and outputting a timing signal equal to a predetermined number of said main clock signals; output control means for generating an output control signal comprised of "0" data and "1" data according to said output data, said "0" data and "1" data being expressed by different combinations of high level period and low level period, in response to said timing signal, wherein said output control means includes: an address selection circuit for decoding an address signal output by said CPU section and selecting an address of said output data storage unit, a parallel-to-serial circuit for time sequentially outputting the data in said output data storage unit at an address selected by said address selection circuit, and a one-data variable counter receiving a logical AND between an output from said count unit and an output from said parallel-to-serial circuit at said selected address and outputting said output control signal; signal output means, receiving said main clock signal and said output control signal, for outputting said main clock signal intermittently in response to a level change of said output control signal; and conversion means for receiving said intermittent main clock signal and generating a remote control signal.
Claim 8
Dependent Claim
19 words
A remote control commander according to claim 5, wherein said conversion means is means for converting into infrared light.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1996-03-08 | 1996-09-07 | 1997-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-08 | 2000-09-07 | 2001-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-08 | 2004-09-07 | 2005-03-09 | $7700.00 | Window Closed / Lapsed |