US5189418A
Expired / Lapsed
US
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Dither error correction
Assignee: Agilent Technologies Inc
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Filing: 1992-04-16
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Granted: 1993-02-23
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Expires: 2012-04-16
Abstract
Abstract A technique for correcting settling, feedthru, and higher order error mechanisms in a dithered analog-to-digital conversion circuit is disclosed. For each conversion cycle of an ADC, a dither signal is generated by converting a current dither value from a sequence of dither values and is then added to an analog input signal. The analog input signal and dither signal are converted by the ADC, and the current dither value subtracted, to form a digital output signal. Correction signals proportional to dither values which precede or follow the current dither value in the sequence are also generated each conversion cycle and subtracted from the analog input signal. The proportions used to produce the correction signals are adjusted dynamically according to the amount of correlation between the digital output signal and the dither values used to form the correction signals. The correction signals are thereby made to equal the amount of error contributed by a corresponding one of the error mechanisms.
Inventors
- 👤 Manfred U. Bartz
- 👤 Donald R. Hiller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:18
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0634; H03M1/0636; H03M1/0639; H03M1/0641; H03M1/12
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
140 words
A dithered analog-to-digital conversion circuit with component limitation error correction, comprising: a PRN generator for digitally generating a sequence of dither values; a dither DAC connected to the PRN generator for sequentially converting the dither values to analog form to produce an analog dither signal; an input for receiving an analog input signal; at least one generating means coupled to the PRN generator, each generating means generating a correction signal; summing means for combining the analog input signal and the analog dither signal to produce a combined signal, and for subtracting each correction signal from a dither signal path; an analog-to-digital converter for converting the combined signal to digital form; and a digital dither subtractor coupled to an output of the analog-to-digital converter for subtracting the sequence of dither values from the combined signal to produce a digital output signal.
Claim 2
Dependent Claim
140 words
A dithered analog-to-digital conversion circuit with component limitation error correction, comprising: a PRN generator for digitally generating a sequence of dither values; a dither DAC connected to the PRN generator for sequentially converting the dither values to analog form to produce an analog dither signal; an input for receiving an analog input signal; at least one generating means coupled to the PRN generator, each generating means generating a correction signal; summing means for combining the analog input signal and the analog dither signal to produce a combined signal, and for subtracting each correction signal from a dither signal path; an analog-to-digital converter for converting the combined signal to digital form; and a digital dither subtractor coupled to an output of the analog-to-digital converter for subtracting the sequence of dither values from the combined signal to produce a digital output signal.
Claim 3
Dependent Claim
111 words
The dithered analog-to-digital circuit of claim 1, wherein each generating means comprises: a correction DAC for sequentially converting the dither values to analog form to produce said correction signal, the correction DAC converting a first dither value concurrently with the dither DAC converting a current dither value, the first dither value being offset a predetermined number of dither values from the current dither value in the sequence of dither values; a delay latch associated with the correction DAC for separating the first dither value from the sequence of dither values; and a scaling block coupled to an output of the correction DAC for multiplying the correction signal by a gain constant.
Claim 4
Dependent Claim
42 words
The dithered analog-to-digital circuit of claim 2, wherein the summing means comprises an analog summing node for adding the analog dither signal to the analog input signal to form the combined signal, and for subtracting each correction signal from the combined signal.
Claim 5
Dependent Claim
38 words
The dithered analog-to-digital circuit of claim 2 wherein the summing means for subtracting each correction signal from a dither signal path comprises at least one digital subtractor connected to the dither signal path after the digital dither subtractor.
Claim 6
Dependent Claim
98 words
The dithered analog-to-digital conversion circuit of claim 2, wherein each generating means comprises: a correlator connected to the digital dither subtractor for detecting correlation between the digital output signal and dither values converted by the correction DAC; an accumulator connected to the correlator for producing an accumulated value equal to the amount of correlation detected by the correlator; and a gain control DAC for converting the accumulated value to a gain control signal, the gain control DAC connected to said scaling block to feed-back the gain control signal to said scaling block and thereby adjust said gain constant.
Claim 7
Dependent Claim
67 words
The dithered analog-to-digital conversion circuit of claim 2 for correcting settling errors due to speed limitations of its components wherein the correction DAC of one of the at least one generating means is a settling DAC for converting a first dither value concurrently with the dither DAC converting a current dither value, the first dither value preceding the current dither value in the sequence of dither values.
Claim 8
Dependent Claim
37 words
The dithered analog-to-digital conversion circuit of claim 6 wherein the scaling block of said one of the generating means comprises a difference circuit for subtracting a signal proportional to the current dither value from the correction signal.
Claim 9
Dependent Claim
78 words
The dithered analog-to-digital conversion circuit of claim 1 for correcting settling errors due to speed limitations of its components wherein one of the at least one generating means comprises a settling DAC for, concurrently with the dither DAC converting a current dither value, converting to analog form a value proportional to the difference between a first dither value and the current dither value, the first dither value preceding the current dither value in the sequence of dither values.
Claim 10
Dependent Claim
70 words
The dithered analog-to-digital conversion circuit of claim 2 for correcting feedthru errors due to inadequate input to output isolation of its components wherein the correction DAC of one of the at least one generating means is a feedthru DAC for converting a first dither value concurrently with the dither DAC converting a current dither value, the first dither value following the current dither value in the sequence of dither values.
Claim 11
Dependent Claim
126 words
The dithered analog-to-digital conversion circuit of claim 1 wherein each of the generating means comprises: a correlator connected to the digital dither subtractor for detecting correlation between the digital output signal and the dither values, the correlator detecting correlation between the digital output signal and a first dither value concurrently with the dither DAC converting a current dither value, the first dither value being offset a predetermined number of dither values from the current dither value in the sequence of dither values; an accumulator connected to the correlator for accumulating an amount of correlation detected by the correlator; and a multiplier connected to the accumulator for multiplying the first dither value by a scaling value proportional to the amount of correlation to produce said correction signal.
Claim 12
Dependent Claim
39 words
The dithered analog-to-digital circuit of claim 10, wherein the summing means comprises: at least one digital subtractor coupled between the output of the analog-to-digital converter and the digital dither subtractor for subtracting each correction signal from the combined signal.
Claim 13
Dependent Claim
53 words
The dithered analog-to-digital circuit of claim 10, wherein the summing means comprises: at least one digital subtractor connected to the dither signal path after the digital dither subtractor for subtracting each correction signal from the digital output signal, the at least one digital subtractor corresponding one-to-one with the at least one generating means.
Claim 14
Dependent Claim
43 words
The dithered analog-to-digital circuit of claim 10 wherein the PRN generator, the at least one generating means, the summing means for subtracting each correction signal from a dither signal path, and the digital dither subtractor are digitally implemented in a single integrated circuit.
Claim 15
Independent Claim
145 words
A method of correcting residue errors in a dithered analog-to-digital conversion circuit, comprising: generating a sequence of dither values with a digital PRN generator; converting sequentially said dither values to analog form with a dither DAC to form an analog dither signal; concurrently with the converting of each dither value in said sequence with the dither DAC, generating at least one correction signal, each correction signal proportional to a dither value offset a predetermined number of dither values in the sequence from the dither value currently converted by the dither DAC; summing the analog dither signal with an analog input signal to form a combined signal; converting the combined signal to digital form using an analog-to-digital converter; subtracting the at least one correction signal from a dither signal path; and subtracting the sequence of dither values from the combined signal to form an output signal.
Claim 16
Independent Claim
145 words
A method of correcting residue errors in a dithered analog-to-digital conversion circuit, comprising: generating a sequence of dither values with a digital PRN generator; converting sequentially said dither values to analog form with a dither DAC to form an analog dither signal; concurrently with the converting of each dither value in said sequence with the dither DAC, generating at least one correction signal, each correction signal proportional to a dither value offset a predetermined number of dither values in the sequence from the dither value currently converted by the dither DAC; summing the analog dither signal with an analog input signal to form a combined signal; converting the combined signal to digital form using an analog-to-digital converter; subtracting the at least one correction signal from a dither signal path; and subtracting the sequence of dither values from the combined signal to form an output signal.
Claim 17
Dependent Claim
75 words
The method of claim 14 for also dynamically adjusting the correction signals, comprising for each correction signal; detecting an amount of correlation between the output signal and said dither value offset a predetermined number of dither values in the sequence from the dither value currently converted by the dither DAC; accumulating the amount of correlation; scaling the correction signal by an adjustable gain value; and adjusting said gain value according to the amount of correlation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-02-23 | 1996-08-24 | 1997-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-02-23 | 2000-08-24 | 2001-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-02-23 | 2004-08-24 | 2005-02-23 | $7700.00 | Window Closed / Lapsed |