Process for forming extremely thin edge-connectable integrated circuit structure

Claim 1

A method of forming an edge connector to a semiconductor substrate having comprising the steps of: (a) forming, in said semiconductor substrate, a region of material capable of being bonded with conductive material; (b) forming a trench pattern in a first surface of said semiconductor substrate so as to expose a sidewall portion of said region; (c) bonding conductive material to said sidewall portion of said region; (d) forming a layer of a prescribed material in said trench pattern; (e) mounting said semiconductor substrate on a support member such that the first surface of said semiconductor substrate faces said support member; (f) removing material from a second surface of said semiconductor substrate, opposite to said first surface thereof, so as to effect a thinning of said substrate down to a level which exposes said prescribed material in said trench pattern; (g) removing said prescribed material from said trench pattern, thereby leaving a plurality of spaced apart semiconductor dice that are supported by way of said support member; and (h) removing said plurality of dice from said support member.

Claim 2

A method of forming an edge connector to a semiconductor substrate having comprising the steps of: (a) forming, in said semiconductor substrate, a region of material capable of being bonded with conductive material; (b) forming a trench pattern in a first surface of said semiconductor substrate so as to expose a sidewall portion of said region; (c) bonding conductive material to said sidewall portion of said region; (d) forming a layer of a prescribed material in said trench pattern; (e) mounting said semiconductor substrate on a support member such that the first surface of said semiconductor substrate faces said support member; (f) removing material from a second surface of said semiconductor substrate, opposite to said first surface thereof, so as to effect a thinning of said substrate down to a level which exposes said prescribed material in said trench pattern; (g) removing said prescribed material from said trench pattern, thereby leaving a plurality of spaced apart semiconductor dice that are supported by way of said support member; and (h) removing said plurality of dice from said support member.

Claim 14

A method of forming a metallic link to a sidewall portion of a semiconductor wafer comprising the steps of: (a) forming, in a first surface said wafer, a region of a metallic layer; (b) attaching an electrode layer to a first portion of said region; (c) forming a trench pattern in said first surface of said wafer, so as to expose a sidewall portion of said region, spaced apart from said first portion thereof; (d) electroplating a metallic layer onto said sidewall portion of said region, using said electro layer as an electroplating electrode, while placing said side portion of said region in contact with an electroplating solution; (e) filling said trench pattern with a trench fill material the resistance of which to physical removal is greater than that of said semiconductor wafer; (f) adhering said semiconductor wafer, a first surface down, onto a planar support member; (g) removing, by mechanical polishing, material from a second surface of said planar semiconductor wafer, opposite to said first surface, so as to effect a thinning of said wafer down to a level which exposes said trench fill material; (h) removing said trench fill material from said trench pattern, so that a plurality of spaced-apart semiconductor dice are supported by way of said support member; and (i) removing said plurality of dice from said support member.

Claim 15

A method of forming a metallic link to a sidewall portion of a semiconductor wafer comprising the steps of: (a) forming, in a first surface said wafer, a region of a metallic layer; (b) attaching an electrode layer to a first portion of said region; (c) forming a trench pattern in said first surface of said wafer, so as to expose a sidewall portion of said region, spaced apart from said first portion thereof; (d) electroplating a metallic layer onto said sidewall portion of said region, using said electro layer as an electroplating electrode, while placing said side portion of said region in contact with an electroplating solution; (e) filling said trench pattern with a trench fill material the resistance of which to physical removal is greater than that of said semiconductor wafer; (f) adhering said semiconductor wafer, a first surface down, onto a planar support member; (g) removing, by mechanical polishing, material from a second surface of said planar semiconductor wafer, opposite to said first surface, so as to effect a thinning of said wafer down to a level which exposes said trench fill material; (h) removing said trench fill material from said trench pattern, so that a plurality of spaced-apart semiconductor dice are supported by way of said support member; and (i) removing said plurality of dice from said support member.

Claim 22

A method of manufacturing a semiconductor device comprising the steps of: (a) providing a substrate having a semiconductor layer containing integrated circuit components formed in a first planar surface thereof, a passivating layer being formed on said first planar surface so as to extend over integrated circuit components therebeneath, and having a buried insulator layer formed beneath said integrated circuit components, said substrate having material beneath said buried insulator layer; (b) forming a trench pattern through said passivating layer and the thickness of said semiconductor layer down to said buried insulator layer; (c) forming a conductive layer onto a sidewall portion of said trench pattern; (d) filling said trench pattern with a prescribed trench fill material; (e) mounting the structure resulting from step (d) on a support member such that the first planar surface of said semiconductor layer faces said support member; (f) removing said material of said substrate beneath said buried insulator layer so as to expose said buried insulator layer; (g) removing said buried insulator layer, thereby exposing said trench fill material in said trench pattern; (h) removing said trench fill material from said trench pattern, so that a plurality of spaced apart semiconductor dice are supported by way of said support member; and (i) removing said plurality of dice from said support member.

Claim 23

A method of manufacturing a semiconductor device comprising the steps of: (a) providing a substrate having a semiconductor layer containing integrated circuit components formed in a first planar surface thereof, a passivating layer being formed on said first planar surface so as to extend over integrated circuit components therebeneath, and having a buried insulator layer formed beneath said integrated circuit components, said substrate having material beneath said buried insulator layer; (b) forming a trench pattern through said passivating layer and the thickness of said semiconductor layer down to said buried insulator layer; (c) forming a conductive layer onto a sidewall portion of said trench pattern; (d) filling said trench pattern with a prescribed trench fill material; (e) mounting the structure resulting from step (d) on a support member such that the first planar surface of said semiconductor layer faces said support member; (f) removing said material of said substrate beneath said buried insulator layer so as to expose said buried insulator layer; (g) removing said buried insulator layer, thereby exposing said trench fill material in said trench pattern; (h) removing said trench fill material from said trench pattern, so that a plurality of spaced apart semiconductor dice are supported by way of said support member; and (i) removing said plurality of dice from said support member.

Claim 27

A method of conductively connecting an array of photoresponsive devices that are supported within a first semiconductor substrate and for which respective conductive land portions are provided over a first surface of said first semiconductor substrate, to signal processing devices that are supported in a second semiconductor substrate comprising the steps of: (a) forming, in said second semiconductor substrate, a plurality of regions of material capable of being plated with respective metallic layers and providing conductive connections between said regions and signal processing devices that are supported within said second semiconductor substrate; (b) forming a trench pattern in said second semiconductor substrate, so as to expose respective sidewall portions of said regions; (c) plating respective metallic layers to the respective sidewall portions of said regions and thereby providing a plurality of metallic land portions at sidewall portions of said second semiconductor substrate that are conductively connected to said plurality of signal processing devices supported therein; (d) forming a layer of a prescribed material in said trench pattern; (e) mounting said second semiconductor substrate on a support member such that the first surface of said second semiconductor substrate faces said support member; (f) removing material from a second surface of said second semiconductor substrate, opposite to said first surface thereof, so as to effect a thinning of said second semiconductor substrate down to a level which exposes said prescribed material in said trench pattern; (g) removing said prescribed material from said trench pattern, thereby leaving a plurality of spaced apart semiconductor dice that are supported by way of said support member; (h) removing said plurality of dice from said support member; and (i) bringing a side edge portion of a die removed in step (h) into adjacent alignment with plural conductive land portions of said first semiconductor substrate and conductively joining said plural conductive land portions of said first semiconductor substrate with plural metallic layers that have been plated to side portions of regions of said die in step (c).

Claim 28

A method of conductively connecting an array of photoresponsive devices that are supported within a first semiconductor substrate and for which respective conductive land portions are provided over a first surface of said first semiconductor substrate, to signal processing devices that are supported in a second semiconductor substrate comprising the steps of: (a) forming, in said second semiconductor substrate, a plurality of regions of material capable of being plated with respective metallic layers and providing conductive connections between said regions and signal processing devices that are supported within said second semiconductor substrate; (b) forming a trench pattern in said second semiconductor substrate, so as to expose respective sidewall portions of said regions; (c) plating respective metallic layers to the respective sidewall portions of said regions and thereby providing a plurality of metallic land portions at sidewall portions of said second semiconductor substrate that are conductively connected to said plurality of signal processing devices supported therein; (d) forming a layer of a prescribed material in said trench pattern; (e) mounting said second semiconductor substrate on a support member such that the first surface of said second semiconductor substrate faces said support member; (f) removing material from a second surface of said second semiconductor substrate, opposite to said first surface thereof, so as to effect a thinning of said second semiconductor substrate down to a level which exposes said prescribed material in said trench pattern; (g) removing said prescribed material from said trench pattern, thereby leaving a plurality of spaced apart semiconductor dice that are supported by way of said support member; (h) removing said plurality of dice from said support member; and (i) bringing a side edge portion of a die removed in step (h) into adjacent alignment with plural conductive land portions of said first semiconductor substrate and conductively joining said plural conductive land portions of said first semiconductor substrate with plural metallic layers that have been plated to side portions of regions of said die in step (c).

Claim 32

A method of manufacturing an opto-electronic imaging system comprising the steps of: (a) providing a first semiconductor substrate having formed in a first surface thereof a matrix of rows and columns of photoresponsive devices and having extending from a second surface thereof an associated matrix of conductive land portions that are electrically coupled with respective ones of said photoresponsive devices; (b) providing, for each row of said matrix of photoresponsive devices, a respective second semiconductor substrate having a semiconductor layer containing integrated circuit components formed in a first planar surface thereof which are interconnected to form signal processing devices for processing the outputs of an associated row of said matrix of photoresponsive devices, said second semiconductor substrate having a passivating layer formed on said first planar surface so as to extend over integrated circuit components therebeneath, and having a buried insulator layer formed beneath said integrated circuit components, said substrate having material beneath said buried insulator layer; (c) forming a trench pattern through said passivating layer and the thickness of said semiconductor layer down to said buried insulator layer, so as to separate said semiconductor layer into a plurality of semiconductor dice supported on said buried insulator layer; (d) plating a plurality of metallic bumps on sidewalls of said trench pattern, said metallic bumps being conductively connected to signal processing devices within said second semiconductor substrate; (e) forming etch resistant material on said passivating layer and on sidewalls of said trench pattern, with a floor portion of said trench pattern exposing said buried insulator layer; (f) applying an etchant to said buried insulator layer by way of the exposed floor portion of said trench pattern, so as to etch away said buried insulator layer and thereby remove said plurality of semiconductor dice from substrate material beneath said buried insulator layer. (g) bringing the side edge portion of a respective removed die into adjacent alignment with plural conductive land portions of said first semiconductor substrate and conductively joining said plural conductive land portions of said first semiconductor substrate with plural metallic bumps along side portions of said respective dice.

Claim 33

A method of manufacturing an opto-electronic imaging system comprising the steps of: (a) providing a first semiconductor substrate having formed in a first surface thereof a matrix of rows and columns of photoresponsive devices and having extending from a second surface thereof an associated matrix of conductive land portions that are electrically coupled with respective ones of said photoresponsive devices; (b) providing, for each row of said matrix of photoresponsive devices, a respective second semiconductor substrate having a semiconductor layer containing integrated circuit components formed in a first planar surface thereof which are interconnected to form signal processing devices for processing the outputs of an associated row of said matrix of photoresponsive devices, said second semiconductor substrate having a passivating layer formed on said first planar surface so as to extend over integrated circuit components therebeneath, and having a buried insulator layer formed beneath said integrated circuit components, said substrate having material beneath said buried insulator layer; (c) forming a trench pattern through said passivating layer and the thickness of said semiconductor layer down to said buried insulator layer, so as to separate said semiconductor layer into a plurality of semiconductor dice supported on said buried insulator layer; (d) plating a plurality of metallic bumps on sidewalls of said trench pattern, said metallic bumps being conductively connected to signal processing devices within said second semiconductor substrate; (e) forming etch resistant material on said passivating layer and on sidewalls of said trench pattern, with a floor portion of said trench pattern exposing said buried insulator layer; (f) applying an etchant to said buried insulator layer by way of the exposed floor portion of said trench pattern, so as to etch away said buried insulator layer and thereby remove said plurality of semiconductor dice from substrate material beneath said buried insulator layer. (g) bringing the side edge portion of a respective removed die into adjacent alignment with plural conductive land portions of said first semiconductor substrate and conductively joining said plural conductive land portions of said first semiconductor substrate with plural metallic bumps along side portions of said respective dice.