US5179714A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallel bit serial data processor
Assignee: Xylon LLC
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Filing: 1988-10-07
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Granted: 1993-01-12
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Expires: 2008-10-07
Abstract
Abstract A single instruction multiple data systolic array processor having provision for local address generation, direct access to external devices, and programmable cell interconnectivity for providing great versatility while at the same time retaining the advantages of the SIMD architecture.
Inventors
- 👤 Robert B. Graybill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:11
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8046
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
167 words
A parallel data processor comprising: first means for generating control signals and address data; and a plurality of substantially identical processing cell means, for processing data one bit at a time, each of the cell means being connected to at least two other cell means, and each of the cell means including: (a) second means, internal to the cell means and responsive to said control signals, for generating effective address data based on said address data, (b) memory means, responsive to said first means and to said second means, for storing or retrieving one bit of data at addresses indicated by said effective address data and for storing said address data, and (c) third means, responsive to the memory means, for performing arithmetic operations on address data supplied by the memory means and for supplying results of said arithmetic operations to said second means, wherein said third means is for adding a first value indicative of an address and a second value indicative of an address offset.
Claim 2
Dependent Claim
167 words
A parallel data processor comprising: first means for generating control signals and address data; and a plurality of substantially identical processing cell means, for processing data one bit at a time, each of the cell means being connected to at least two other cell means, and each of the cell means including: (a) second means, internal to the cell means and responsive to said control signals, for generating effective address data based on said address data, (b) memory means, responsive to said first means and to said second means, for storing or retrieving one bit of data at addresses indicated by said effective address data and for storing said address data, and (c) third means, responsive to the memory means, for performing arithmetic operations on address data supplied by the memory means and for supplying results of said arithmetic operations to said second means, wherein said third means is for adding a first value indicative of an address and a second value indicative of an address offset.
Claim 3
Dependent Claim
27 words
A parallel data processor as claimed in claim 1, wherein said second means comprises a counter, and wherein said third means comprises a one-bit arithmetic logic unit.
Claim 4
Dependent Claim
29 words
A parallel data processor as claimed in claim 2, wherein a summing output of said arithmetic logic unit is connected to a serial input and output of said counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-12 | 1996-07-13 | 1997-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-12 | 2000-07-13 | 2001-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-12 | 2004-07-13 | 2005-01-12 | $7700.00 | Window Closed / Lapsed |