US5177786A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for scrambling/descrambling a video signal
Assignee: LG Electronics Inc
•
Filing: 1991-04-30
•
Granted: 1993-01-05
•
Expires: 2011-04-30
Abstract
Abstract A method and an apparatus for scrambling and descrambling a composite video signal. The method comprises the steps of multiplying a digitalized composite video signal by a transform matrix of a predetermined format in order to bit-scramble them and multiplying the bit-scrambled signals by a matrix of the reverse of said predetermined format to descramble them into original composite video signals. The apparatus comprises a plurality of multiplexers adapted to scramble and descramble the digitized composite video signal in response to external select signals. The external select signals which are applied to the multiplexers of a descrambler 2'S complement signals of signals applied to multiplexers in a scrambler. According to the present method and apparatus, it is possible to prevent any deterioration of the image quality, increase of cost, and illegal watching by non-subscribers.
Inventors
- 👤 Kyung J. Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:19
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/10; H04N7/16; H04N7/167; H04N7/169; H04N7/1696; H04N21/00; H04N21/20; H04N21/23; H04N21/234; H04N21/2347; H04N21/40; H04N21/43; H04N21/44; H04N21/4405; H04N7/1675
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
311 words
An apparatus for scrambling a video signal comprising: an A/D converter for receiving a composite video signal and for converting the composite video signal into a digital signal for bit-scrambling; a multiplexing means for receiving the digital signal from said A/D converter and for multiplexing the digital signal in response to an external select signal; a D/A converter for receiving the multiplexed digital signal from said multiplexing means and for converting the multiplexed digital signal into an analog signal; a synchronous divider for receiving said composite video signal and for dividing the composite video signal into a vertical synchronizing signal and a horizontal synchronizing signal; a clock generator for receiving the horizontal synchronizing signal from said synchronous divider to generate a clock signal and for supplying the clock signal to said A/D converter and said D/A converter; an initial data generating means for receiving said composite video signal, for extracting from said composite video signal initial data coded during a vertical blanking interval thereof for each field thereof, and for decoding the extracted coded initial data; a horizontal blanking interval detector for receiving the horizontal synchronizing signal from said synchronous divider, for detecting a horizontal blanking interval from said horizontal synchronizing signal, and for outputting a low signal during the detected horizontal blanking interval; a random number generator for generating pseudorandom numbers of a predetermined number of bits, upon receiving the vertical synchronizing signal from said synchronous divider and the decoded initial data from said initial data generating means; and an AND logic operating means including a plurality of AND gates where each gate has a first input terminal for receiving each bit signal from said random number generator, a second input terminal for receiving an output signal from said horizontal blanking interval detector and an output terminal coupled in common to said multiplexing means for applying said external select signal.
Claim 2
Independent Claim
311 words
An apparatus for scrambling a video signal comprising: an A/D converter for receiving a composite video signal and for converting the composite video signal into a digital signal for bit-scrambling; a multiplexing means for receiving the digital signal from said A/D converter and for multiplexing the digital signal in response to an external select signal; a D/A converter for receiving the multiplexed digital signal from said multiplexing means and for converting the multiplexed digital signal into an analog signal; a synchronous divider for receiving said composite video signal and for dividing the composite video signal into a vertical synchronizing signal and a horizontal synchronizing signal; a clock generator for receiving the horizontal synchronizing signal from said synchronous divider to generate a clock signal and for supplying the clock signal to said A/D converter and said D/A converter; an initial data generating means for receiving said composite video signal, for extracting from said composite video signal initial data coded during a vertical blanking interval thereof for each field thereof, and for decoding the extracted coded initial data; a horizontal blanking interval detector for receiving the horizontal synchronizing signal from said synchronous divider, for detecting a horizontal blanking interval from said horizontal synchronizing signal, and for outputting a low signal during the detected horizontal blanking interval; a random number generator for generating pseudorandom numbers of a predetermined number of bits, upon receiving the vertical synchronizing signal from said synchronous divider and the decoded initial data from said initial data generating means; and an AND logic operating means including a plurality of AND gates where each gate has a first input terminal for receiving each bit signal from said random number generator, a second input terminal for receiving an output signal from said horizontal blanking interval detector and an output terminal coupled in common to said multiplexing means for applying said external select signal.
Claim 3
Dependent Claim
83 words
An apparatus for scrambling a video signal as claimed in claim 1, wherein said initial data generating means includes a data slicer for extracting from said composite video signal said initial data coded during the vertical blanking interval thereof for each field thereof, a data RAM for storing said coded initial data from said data slicer, and a microprocessor for decoding said coded initial data stored in said data RAM and for sending the decoded initial data out to said random number generator.
Claim 4
Dependent Claim
95 words
An apparatus for scrambling a video signal as claimed in claim 1, wherein said multiplexing means includes a first shift register for shifting the digital signal from said A/D converter to the right, a buffer for buffering the digital signal from said A/D converter, a second shift register for shifting the digital signal from said A/D converter to the left, and a switch responsive to said external select signal for selecting the shifted digital signal from said first shift register or said second shift register or for selecting said stored digital signal from said buffer.
Claim 5
Independent Claim
327 words
An apparatus for descrambling a video signal comprising; an A/D converter for receiving a scrambled composite video signal and for converting the composite video signal into a digital signal for descrambling; a multiplexing means for receiving the digital signal from said A/D converter and for multiplexing the digital signal in response to an external select signal; a D/A converter for receiving the multiplexed digital signal from said multiplexing means and for converting the multiplexed digital signal into an analog signal; a synchronous divider for receiving said composite video signal and for dividing the composite video signal into a vertical synchronizing signal and a horizontal synchronizing signal; a clock generator for receiving the horizontal synchronizing signal from said synchronous divider to generate a clock signal and for supplying the clock signal to said A/D converter and said D/A converter; an initial data generating means for receiving said composite video signal, for extracting from said composite video signal initial data coded during a vertical blanking interval thereof for each field thereof, and for decoding the extracted coded initial data; a horizontal blanking interval detector for receiving the horizontal synchronizing signal from said synchronous divider, for detecting a horizontal blanking interval from said horizontal synchronizing signal, and for outputting a low signal during the detected horizontal blanking interval; a random number generator for generating pseudorandom numbers of a predetermined number of bits, upon receiving the vertical synchronizing signal from said synchronous divider and the decoded initial data from said initial data generating means; a 2'S complement converter for complementing each bit signal from said random number generator; and an AND logic operating means including a plurality of AND gates where each gate has a first input terminal for receiving each complemented bit signal from said 2'S complement converter, a second input terminal for receiving an output signal from said horizontal blanking interval detector and an output terminal coupled in common to said multiplexing means for applying said external select signal.
Claim 6
Independent Claim
327 words
An apparatus for descrambling a video signal comprising; an A/D converter for receiving a scrambled composite video signal and for converting the composite video signal into a digital signal for descrambling; a multiplexing means for receiving the digital signal from said A/D converter and for multiplexing the digital signal in response to an external select signal; a D/A converter for receiving the multiplexed digital signal from said multiplexing means and for converting the multiplexed digital signal into an analog signal; a synchronous divider for receiving said composite video signal and for dividing the composite video signal into a vertical synchronizing signal and a horizontal synchronizing signal; a clock generator for receiving the horizontal synchronizing signal from said synchronous divider to generate a clock signal and for supplying the clock signal to said A/D converter and said D/A converter; an initial data generating means for receiving said composite video signal, for extracting from said composite video signal initial data coded during a vertical blanking interval thereof for each field thereof, and for decoding the extracted coded initial data; a horizontal blanking interval detector for receiving the horizontal synchronizing signal from said synchronous divider, for detecting a horizontal blanking interval from said horizontal synchronizing signal, and for outputting a low signal during the detected horizontal blanking interval; a random number generator for generating pseudorandom numbers of a predetermined number of bits, upon receiving the vertical synchronizing signal from said synchronous divider and the decoded initial data from said initial data generating means; a 2'S complement converter for complementing each bit signal from said random number generator; and an AND logic operating means including a plurality of AND gates where each gate has a first input terminal for receiving each complemented bit signal from said 2'S complement converter, a second input terminal for receiving an output signal from said horizontal blanking interval detector and an output terminal coupled in common to said multiplexing means for applying said external select signal.
Claim 7
Dependent Claim
83 words
An apparatus for descrambling a video signal as claimed in claim 4, wherein said initial data generating means includes a data slicer for extracting from said composite video signal said initial data coded during the vertical blanking interval thereof for each field thereof, a data RAM for storing said coded initial data from said data slicer, and a microprocessor for decoding said coded initial data stored in said data RAM and for sending the decoded initial data out to said random number generator.
Claim 8
Dependent Claim
95 words
An apparatus for descrambling a video signal as claimed in claim 4, wherein said multiplexing means includes a first shift register for shifting the digital signal from said A/D converter to the left, a buffer for buffering the digital signal from said A/D converter, a second shift register for shifting the digital signal from said A/D converter to the right, and a switch responsive to said external select signal for selecting the shifted digital signal from said first shift register or said second shift register or for selecting said stored digital signal from said buffer.
Claim 9
Independent Claim
107 words
A method of scrambling, transmitting and descrambling a video signal comprising the steps of: converting a composite video signal into digital signals of a predetermined number of bits and multiplying the digital signals by a transform matrix of a predetermined format to bit-scramble them; converting said bit-scrambled digital signals to an analog signal and transmitting the analog-converted signal to a user station; re-converting said analog-converted signal into digital signals of said predetermined number of bits and multiplying the digital signals by an alternative transform matrix of the reverse of said predetermined format to descramble them; and converting said descrambled digital signals to an original composite video signal.
Claim 10
Independent Claim
107 words
A method of scrambling, transmitting and descrambling a video signal comprising the steps of: converting a composite video signal into digital signals of a predetermined number of bits and multiplying the digital signals by a transform matrix of a predetermined format to bit-scramble them; converting said bit-scrambled digital signals to an analog signal and transmitting the analog-converted signal to a user station; re-converting said analog-converted signal into digital signals of said predetermined number of bits and multiplying the digital signals by an alternative transform matrix of the reverse of said predetermined format to descramble them; and converting said descrambled digital signals to an original composite video signal.
Claim 11
Dependent Claim
86 words
A method for scrambling, transmitting and descrambling a video signal as claimed in claim 7, wherein said transform matrix is defined by n expressed by the equations: ##EQU2## such that: =π.sub.n ; and =π.sub.a-n ; where: =a matrix of the bit-scrambled digitized signal; =a matrix of the digitized signal; a=the predetermined number of bits in said digitized signal; j=positive integer from 1 to a; k=positive integer from 1 to a; n=random positive integer including zero; Ra(j+n)=the remainder of (j+n)/a, but, when the remainder is zero, Ra(j+n)=a.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-05 | 1996-07-06 | 1997-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-05 | 2000-07-06 | 2001-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-05 | 2004-07-06 | 2005-01-05 | $7700.00 | Window Closed / Lapsed |