US5177707A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory with improved reading time
Assignee: STMicroelectronics SA
•
Filing: 1990-10-01
•
Granted: 1993-01-05
•
Expires: 2010-10-01
Abstract
Abstract To shorten the reading cycle of a memory, the memory cells of which comprise floating gate transistors, a circuit for pre-charging the bit lines of the memory is used, this circuit being independent of the reading sense amplifier proper. This pre-charging circuit includes a differential amplifier receiving, firstly, a voltage signal for the effective pre-charging of the bit line and, secondly, a pre-charging voltage reference signal. So long as the effective pre-charging has not reached the assigned value, the differential amplifier delivers a command signal to a power transistor that pre-charges the bit lines. As soon as the assigned pre-charging value is reached, the power transistor goes off, and the circuit of the amplifier is itself uncoupled.
Inventors
- 👤 Franck Edme
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:09
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/24; G11C7/00; G11C7/10; G11C7/1048
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
127 words
A memory comprising: a plurality of memory cells, each of which includes a floating gate transistor; bit lines to gain access to said memory cells; means for pre-charging said bit lines before a reading of memory cell electrical states; a differential amplifier receiving a pre-charging voltage reference signal to be compared with a voltage corresponding to an effective pre-charging of said bit lines, said differential amplifier delivering a charging command signal; said means for pre-charging said bit-lines comprising a power transistor activated by said command signal for pre-charging said bit lines; said power transistor having a drain, a source, and a gate, and being serially connected by its drain and source between a power supply and said bit lines, and receiving on its gate said command signal.
Claim 2
Dependent Claim
127 words
A memory comprising: a plurality of memory cells, each of which includes a floating gate transistor; bit lines to gain access to said memory cells; means for pre-charging said bit lines before a reading of memory cell electrical states; a differential amplifier receiving a pre-charging voltage reference signal to be compared with a voltage corresponding to an effective pre-charging of said bit lines, said differential amplifier delivering a charging command signal; said means for pre-charging said bit-lines comprising a power transistor activated by said command signal for pre-charging said bit lines; said power transistor having a drain, a source, and a gate, and being serially connected by its drain and source between a power supply and said bit lines, and receiving on its gate said command signal.
Claim 3
Dependent Claim
66 words
A memory according to claim 1, including a simulating circuit comprising a resistance connected by one first end to a first end of a capacitor, said resistance being connected by said first end to an input of said differential amplifier and by another end to said power supply, said capacitor being connected by a second end to ground, said simulating circuit simulating an effective pre-charging voltage.
Claim 4
Dependent Claim
25 words
A memory according to claim 1 or claim 2 comprising a circuit to connect the bit lines to one another at the time of pre-charging.
Claim 5
Dependent Claim
36 words
A memory according to claim 1 or claim 2 wherein the differential amplifier includes, for comparison, two transistors so as to introduce no error into the comparison of the reference voltage with the effective pre-charging voltage.
Claim 6
Dependent Claim
45 words
A memory according to claim 1 or claim 2 including a circuit to uncouple the differential amplifier at the time of reading electrical states, to prevent maintenance of a voltage on the bit lines due to the presence of stray capacitance from said differential amplifier.
Claim 7
Dependent Claim
44 words
A memory according to claim 1 or claim 2 including a circuit for reading the electrical states, said reading circuit including a transistor divider bridge and a switching transistor to connect a midpoint of the bridge in circuit with the bit lines during pre-charging.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-05 | 1996-07-06 | 1997-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-05 | 2000-07-06 | 2001-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-05 | 2004-07-06 | 2005-01-05 | $7700.00 | Window Closed / Lapsed |