Digital phase and amplitude modulator

Claim 2

A digital modulator for modulating a stream of incoming data bits in which a predetermined number of such bits, constituting a set, corresponds to a symbol, comprising: (a) means for storing each incoming set of symbol bits, where there is at least one bit in each set, of "n" successive symbols where "n" is a positive integer with a value greater than or equal to 1, with the oldest stored set being discarded upon the arrival and storage of a next set of symbol bits; (b) memory means for storing sample values corresponding to a modulated symbol impulse response for each of a predetermined number of symbols wherein the modulated symbol impulse responses each extend over "n" symbol periods; (c) means for retrieving sample values over one symbol period from said memory means for overlapping portions of each of the modulated symbol impulse responses stored in said storing means; (d) summing means for summing the sample values which correspond to each other in time for each of the modulated symbol impulse responses corresponding to the received symbols; and (e) converter means for converting summed digital sample values to an analog signal for subsequent transmission.

Claim 3

A modulator according to claim 1, wherein said storing means is a shift register.

Claim 4

A modulator according to claim 1, wherein said memory means is programmable semiconductor memory array.

Claim 5

A modulator according to claim 1, wherein said converter means is a digital to analog converter.

Claim 6

A modulator according to claim 1, wherein said retrieving means includes a decoder having "n" symbol inputs and a counter having sufficient least significant bit lines coupled to a select input to said decoder so that data on any one of the "n" symbol bus lines applied to symbol inputs of said decoder may be selected and applied as most significant address bits to said memory means and least significant bit lines of said counter are applied as least significant address bits to said memory means.

Claim 7

A digital modulator for modulating a stream of incoming data bits in which a predetermined number of successively incoming ones of such bits, constituting a set, correspond to a symbol, comprising: (a) means for temporarily storing, in parallel, incoming symbol data bits of "n" successive symbols where "n" is a positive integer with a value greater than or equal to 1, with the oldest stored symbol bits being discarded upon the arrival and storage of a next set of symbol bits; (b) memory means for storing sample values corresponding to a modulated symbol impulse response for each of a predetermined number of symbols wherein the modulated symbol impulse responses each extend over "n" symbol periods; (c) means for retrieving, in sequence, sample values from said memory means corresponding to symbols stored in said storing means in pre-selected time intervals over a symbol period for overlapping portions of each of the modulated symbol impulse responses corresponding to the symbols stored in said storing means; (d) an adder coupled to said retrieving means and operative to sum the retrieved sample values which correspond to each other in time; and (e) a digital to analog converter coupled to an output of said summing means and operative to convert each sum of sample values for each symbol period to an analog signal for subsequent transmission.

Claim 8

A digital modulator for modulating a stream of incoming data bits in which a predetermined number of successively incoming ones of such bits, constituting a set, correspond to a symbol, comprising: (a) means for temporarily storing, in parallel, incoming symbol data bits of "n" successive symbols where "n" is a positive integer with a value greater than or equal to 1, with the oldest stored symbol bits being discarded upon the arrival and storage of a next set of symbol bits; (b) memory means for storing sample values corresponding to a modulated symbol impulse response for each of a predetermined number of symbols wherein the modulated symbol impulse responses each extend over "n" symbol periods; (c) means for retrieving, in sequence, sample values from said memory means corresponding to symbols stored in said storing means in pre-selected time intervals over a symbol period for overlapping portions of each of the modulated symbol impulse responses corresponding to the symbols stored in said storing means; (d) an adder coupled to said retrieving means and operative to sum the retrieved sample values which correspond to each other in time; and (e) a digital to analog converter coupled to an output of said summing means and operative to convert each sum of sample values for each symbol period to an analog signal for subsequent transmission.

Claim 9

A modulator according to claim 6, wherein said storing means is a shift register.

Claim 10

A modulator according to claim 6, wherein said memory means is programmable, non-volatile semiconductor memory array.

Claim 11

A modulator according to claim 6, wherein said digital to analog converter is provided with an offset which rises linearly to a maximum at a central lobe of an envelope of an impulse response and is substantially horizontal for the side lobes with an average summed value equal to the mid range of the digital to analog converter.

Claim 12

A modulator according to claim 6, wherein said retrieving means includes a decoder having "n" symbol bus inputs with each bus having a number of bit lines corresponding to a symbol and a counter having sufficient least significant bit lines coupled to a select input to said decoder so that data on any one of the "n" symbol bus lines applied to symbol inputs of said decoder may be selected and applied as most significant address bits to said memory means and least significant bit lines of said counter are applied as least significant address bits to said memory means.

Claim 13

A digital modulator for modulating a stream of incoming data bits in which a predetermined number of successively incoming ones of such bits correspond to a symbol, comprising: (a) a symbol formatter having an input coupled to said stream of incoming data bits, said formatter operative to arrange incoming symbol bits for each symbol in parallel; (b) a shift register coupled to an output of said symbol formatter having "n" stages for storing in parallel incoming symbol bits of "n" successive symbols where "n" is a positive integer with a value greater than or equal to 1, with the oldest set of stored symbol bits being discarded upon the arrival and storage of a next set of incoming symbol bits; (c) digital semiconductor memory for storing sample values corresponding to a modulated truncated symbol impulse response for each of a predetermined number of symbols wherein the modulated truncated symbol impulse responses each extend over "n" symbol periods; (d) means for retrieving in sequence sample values from said memory corresponding to a given interval of time equal to a symbol period for overlapping portions of each of the modulated truncated symbol impulse responses stored in said storing means; (e) an adder having an input coupled to said memory for summing corresponding sample values received from said memory and operative to add sample values which correspond in time for overlapping portions of each of the modulated truncated symbol impulse responses stored in said memory and corresponding to the symbols stored in said storing means sequentially in predetermined time intervals over a symbol period; and (f) a digital to analog converter means for converting each sum of sample values for each symbol period to an analog signal for subsequent transmission.

Claim 14

A digital modulator for modulating a stream of incoming data bits in which a predetermined number of successively incoming ones of such bits correspond to a symbol, comprising: (a) a symbol formatter having an input coupled to said stream of incoming data bits, said formatter operative to arrange incoming symbol bits for each symbol in parallel; (b) a shift register coupled to an output of said symbol formatter having "n" stages for storing in parallel incoming symbol bits of "n" successive symbols where "n" is a positive integer with a value greater than or equal to 1, with the oldest set of stored symbol bits being discarded upon the arrival and storage of a next set of incoming symbol bits; (c) digital semiconductor memory for storing sample values corresponding to a modulated truncated symbol impulse response for each of a predetermined number of symbols wherein the modulated truncated symbol impulse responses each extend over "n" symbol periods; (d) means for retrieving in sequence sample values from said memory corresponding to a given interval of time equal to a symbol period for overlapping portions of each of the modulated truncated symbol impulse responses stored in said storing means; (e) an adder having an input coupled to said memory for summing corresponding sample values received from said memory and operative to add sample values which correspond in time for overlapping portions of each of the modulated truncated symbol impulse responses stored in said memory and corresponding to the symbols stored in said storing means sequentially in predetermined time intervals over a symbol period; and (f) a digital to analog converter means for converting each sum of sample values for each symbol period to an analog signal for subsequent transmission.

Claim 15

A modulator according to claim 11, wherein said means for retrieving includes a decoder having "n" symbol bus inputs with each bus having a number of bit lines corresponding to a symbol and a counter having sufficient least significant bit lines coupled to a select input to said decoder so that data on any one of the "n" symbol bus lines applied to symbol inputs of said decoder may be selected and applied as most significant address bits to said memory and least significant bit lines of said counter are applied as least significant address bits to said memory.

Claim 16

A modulator according to claim 12, wherein sample values corresponding to each symbol stored in said storing means are retrieved serially from said memory and added by said adder as each said set is retrieved from said memory until sets of values for all symbols stored in said storing means have been added.

Claim 17

A modulator according to claim 11, wherein each symbol impulse response is truncated at a zero crossing at equal time intervals before and after the peak.

Claim 18

A modulator according to claim 11, wherein the modulated symbol impulse response is that as filtered by a cosine filter.

Claim 19

A modulator according to claim 11, wherein varying DC offsets are included in the stored impulse response sample values of a magnitude proportional to the amplitude of each response sample value so that offsets at each of said predetermined time intervals when summed add up to the centre point of the input range of the digital to analog converter.

Claim 20

A modulator according to claim 14, wherein said the stored offsets in the central lobe of the envelope for each store impulse response rises linearly from each side of the lobe to a central maximum.