US5172379A
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High performance memory system
Assignee: EMC Corp
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Filing: 1989-02-24
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Granted: 1992-12-15
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Expires: 2009-02-24
Abstract
Abstract An improved memory system for use in a data processing system which memory system has two memory banks and corresponding error correction circuitry associated with each. Data words of a block thereof are stored in the memory banks in an interleaved fashion wherein alternating words are stored in one bank and intervening alternating words are stored in the other bank. During a write operation the memory is controlled so that the first data word of a block stored in a memory bank uses a late write technique and all subsequent data words thereof use an early write technique. During a read operation, pairs of data words are read and checked for errors simultaneously and are then supplied in a pipelined manner.
Inventors
- 👤 Charlotte A. Burrer
- 👤 Lawrence L. Krantz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:23
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1044; G06F12/00; G06F12/02; G06F12/06; G06F12/0607; G11; G11C; G11C7/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
205 words
A memory system for use in a data processing system comprising two memory banks for storing data words; an error detection and correction means associated with each of said memory banks; means for writing into one of said memory banks, alternating data words of a multi-word data block, and for writing into the other of said memory banks intervening alternating data words of said multi-word data block; means for performing a transfer of said multi-words in a data block thereof so that said data words can be written into said two memory banks in a selected, interleaved sequence; and means for reading a multi-word data block from said memory banks in a pipelined manner such that, with respect to each successive pair of data words of said data block, the data words of each pair are read simultaneously from said memory banks and the data word read from said one memory bank is then made available for a requestor while the data word read form said other memory bank is held prior to being made available for a requestor, the data words when simultaneously read from said memory banks being supplied to the error detecting and correcting means associated with each said memory bank, respectively.
Claim 2
Dependent Claim
205 words
A memory system for use in a data processing system comprising two memory banks for storing data words; an error detection and correction means associated with each of said memory banks; means for writing into one of said memory banks, alternating data words of a multi-word data block, and for writing into the other of said memory banks intervening alternating data words of said multi-word data block; means for performing a transfer of said multi-words in a data block thereof so that said data words can be written into said two memory banks in a selected, interleaved sequence; and means for reading a multi-word data block from said memory banks in a pipelined manner such that, with respect to each successive pair of data words of said data block, the data words of each pair are read simultaneously from said memory banks and the data word read from said one memory bank is then made available for a requestor while the data word read form said other memory bank is held prior to being made available for a requestor, the data words when simultaneously read from said memory banks being supplied to the error detecting and correcting means associated with each said memory bank, respectively.
Claim 3
Dependent Claim
44 words
A memory system in accordance with claim 1 wherein a first data word written into each said memory bank is written using a late write operation and each subsequent data word written into each said memory bank is written using an early write operation.
Claim 4
Dependent Claim
48 words
A memory system in accordance with claim 1 and further wherein, if an error is detected in any data word during a read operation, the read operation is delayed by a selected time period until said error is corrected, said read operation resuming after said selected time period.
Claim 5
Dependent Claim
55 words
A memory system in accordance with claims 2 or 3 wherein said data block comprises four data words, DATA φ-3, data words DATA φ and DATA 2 being written into or read from said one memory bank and data words DATA 1 and DATA 3 being written into or read from said other memory bank.
Claim 6
Dependent Claim
62 words
A memory system in accordance with claims 2 or 4 wherein said data block comprises eight data words, DATA φ-7, data words DATA o, DATA 2, DATA 4, DATA 6 being written into or read form said one memory bank and data words DATA 1, DATA 3, DATA 5, and DATA 7 being written into or read from said other memory bank.
Claim 7
Independent Claim
163 words
A method for writing a block of multiple data words into or reading a block of multiple data words from two memory banks comprising the steps of 1) when writing a block of data words writing into one of said memory banks, alternating data words of said block thereof; and writing into the other of said memory banks, intervening alternating data words of said block thereof; whereby said data words are written into said memory banks in an interleaved sequence thereof; and 2) when reading a block of data words reading pairs of data words simultaneously, one from each memory bank; checking the data words of each of said pair thereof for errors when read; supplying the data words of each pair read from one of said memory banks immediately; and retaining the data word of each pair read from the other of said memory banks for supplying said data word after the data word from said one memory bank has been supplied.
Claim 8
Independent Claim
163 words
A method for writing a block of multiple data words into or reading a block of multiple data words from two memory banks comprising the steps of 1) when writing a block of data words writing into one of said memory banks, alternating data words of said block thereof; and writing into the other of said memory banks, intervening alternating data words of said block thereof; whereby said data words are written into said memory banks in an interleaved sequence thereof; and 2) when reading a block of data words reading pairs of data words simultaneously, one from each memory bank; checking the data words of each of said pair thereof for errors when read; supplying the data words of each pair read from one of said memory banks immediately; and retaining the data word of each pair read from the other of said memory banks for supplying said data word after the data word from said one memory bank has been supplied.
Claim 9
Dependent Claim
50 words
A method in accordance with claim 6, the writing into said memory banks comprises writing the first data word of a block thereof into a memory bank using a late write operation; and writing each subsequent word of said block thereof into a memory bank using an early write operation.
Claim 10
Dependent Claim
42 words
A method in accordance with claim 6 and further comprising delaying the reading of data words from said memory banks by a selected time period when an error has been detected on a data word to permit said error to be corrected.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-15 | 1996-06-15 | 1996-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-15 | 2000-06-15 | 2000-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-15 | 2004-06-15 | 2004-12-15 | $7700.00 | Window Closed / Lapsed |