Semiconductor memory device with increased capacitance of capacitor and manufacturing method thereof

Claim 2

A semiconductor memory device comprising: a semiconductor substrate having a main surface and an oxide film for isolation formed on the main surface; and a memory cell having a transistor and a capacitor, said transistor including a pair of source/drain regions formed in the main surface of said semiconductor substrate and a gate electrode provided on said semiconductor substrate, said capacitor including an interlayer insulation film provided to cover said gate electrode and said isolation oxide film and having an opening for exposing one of said source/drain regions, a conductor layer formed to be in contact with a bottom surface of said opening and to cover said interlayer insulation film, an oxide film provided on said conductor layer and having an opening above and said gate electrode for exposing a portion of said conductor layer, said oxide film having at least one concave portion, a storage node, said concave portion of said oxide film being concave with respect to said storage node, said storage node formed along a sidewall surface and a bottom surface of the opening and the concave portion of said oxide film, a capacitor insulation film provided to cover said storage node, and a cell plate electrode provided to cover said capacitor insulation film.

Claim 3

A semiconductor memory device comprising: a semiconductor substrate having a main surface and an oxide film for isolation formed on the main surface; a memory cell having a transistor and a capacitor, said transistor including a pair of source/drain regions formed in the main surface of said semiconductor substrate and a gate electrode provided on said semiconductor substrate, said capacitor including a first interlayer insulation film provided to cover said gate electrode and said isolation oxide film and having a first opening for exposing one of said source/drain regions, a polysilicon layer provided on the first interlayer insulation film so as to contact one of said source/drain regions through the first opening, a second interlayer insulation film provided on the semiconductor substrate so as to cover the polysilicon layer, said second interlayer insulation film having a second opening overlying said gate electrode, said second opening exposing a portion of the polysilicon layer, a storage node provided on the second interlayer insulation film so as to cover an inner wall surface of the second opening and contact the portion of the polysilicon layer, a capacitor insulation film provided to cover said storage node, and a cell plate electrode provided to cover said capacitor insulation film.

Claim 4

A semiconductor memory device comprising: a semiconductor substrate having a main surface and an oxide film for isolation formed on the main surface; a memory cell having a transistor and a capacitor, said transistor including a pair of source/drain regions formed in the main surface of said semiconductor substrate and a gate electrode provided on said semiconductor substrate, said capacitor including a first interlayer insulation film provided to cover said gate electrode and said isolation oxide film and having a first opening for exposing one of said source/drain regions, a polysilicon layer provided on the first interlayer insulation film so as to contact one of said source/drain regions through the first opening, a second interlayer insulation film provided on the semiconductor substrate so as to cover the polysilicon layer, said second interlayer insulation film having a second opening overlying said gate electrode, said second opening exposing a portion of the polysilicon layer, a storage node provided on the second interlayer insulation film so as to cover an inner wall surface of the second opening and contact the portion of the polysilicon layer, a capacitor insulation film provided to cover said storage node, and a cell plate electrode provided to cover said capacitor insulation film.

Claim 5

A semiconductor memory device comprising: a semiconductor substrate having a main surface and an isolation oxide film formed on the main surface; a memory cell having a transistor and a capacitor, said transistor including a pair of source/drain regions formed in the main surface of said semiconductor substrate and a gate electrode provided on said semiconductor substrate, said capacitor including a first interlayer insulation film covering said gate electrode and said isolation oxide film and having an opening for exposing one of said source/drain regions, a polysilicon layer provided on the first interlayer insulation film so as to contact one of said source/drain regions through said opening, a second interlayer insulation film provided on said semiconductor substrate and covering the polysilicon layer, said second interlayer insulation film having at least one notch exposing a portion of the polysilicon layer above said gate electrode, said at least one notch being substantially perpendicular to the main surface of said semiconductor substrate and including inner wall surfaces, a storage node provided on the second interlayer insulation film covering said inner wall surfaces of said at least one notch and contacting the exposed portion of the polysilicon layer, a capacitor insulation film covering said storage node, and a cell plate electrode covering said capacitor insulation film.

Claim 6

A semiconductor memory device comprising: a semiconductor substrate having a main surface and an isolation oxide film formed on the main surface; a memory cell having a transistor and a capacitor, said transistor including a pair of source/drain regions formed in the main surface of said semiconductor substrate and a gate electrode provided on said semiconductor substrate, said capacitor including a first interlayer insulation film covering said gate electrode and said isolation oxide film and having an opening for exposing one of said source/drain regions, a polysilicon layer provided on the first interlayer insulation film so as to contact one of said source/drain regions through said opening, a second interlayer insulation film provided on said semiconductor substrate and covering the polysilicon layer, said second interlayer insulation film having at least one notch exposing a portion of the polysilicon layer above said gate electrode, said at least one notch being substantially perpendicular to the main surface of said semiconductor substrate and including inner wall surfaces, a storage node provided on the second interlayer insulation film covering said inner wall surfaces of said at least one notch and contacting the exposed portion of the polysilicon layer, a capacitor insulation film covering said storage node, and a cell plate electrode covering said capacitor insulation film.

Claim 7

A semiconductor memory device as recited in claim 3, wherein said second interlayer insulation film includes a second notch exposing a portion of the polysilicon layer located over said opening in said first interlayer insulation film and over at least one of said source/drain regions and said storage node contacts said exposed portion of the polysilicon layer over said at least one of said source/drain regions.

Claim 8

A semiconductor memory device as recited in claim 4, wherein said storage node contacts said exposed portion of the polysilicon layer over both said at least one of said source/drain regions and over said gate electrode.

Claim 9

A semiconductor memory device as recited in claim 5 further comprising an adjacent gate electrode disposed over said isolation oxide film, said adjacent gate electrode forming an adjacent word line, wherein said second interlayer insulation film comprises at least a third notch exposing a portion of the polysilicon layer, said third notch located over said adjacent gate electrode, and wherein said storage node also contacts said exposed portion of the polysilicon layer over said adjacent gate electrode.

Claim 10

A semiconductor memory device as recited in claim 3, wherein said storage node contacts said exposed portion of the polysilicon layer over said gate electrode.

Claim 11

A semiconductor memory device as recited in claim 7 further comprising an adjacent gate electrode disposed over said isolation oxide film, said adjacent gate electrode forming an adjacent word line, wherein said second interlayer insulation film comprises at least a second notch exposing a portion of the polysilicon layer, said second notch located over said adjacent gate electrode, and wherein said storage node also contacts said exposed portion of the polysilicon layer over said adjacent gate electrode.

Claim 12

A semiconductor memory device as recited in claim 3 further comprising an adjacent gate electrode disposed over said isolation oxide film, said adjacent gate electrode forming an adjacent word line, wherein said second interlayer insulation film comprises at least a second notch exposing a portion of the polysilicon layer, said second notch located over said adjacent gate electrode, and wherein said storage node also contacts said exposed portion of the polysilicon layer over said adjacent gate electrode.