US5170371A
Expired / Lapsed
US
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Method and apparatus for rounding in high-speed multipliers
Assignee: Texas Instruments Inc
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Filing: 1988-03-31
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Granted: 1992-12-08
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Expires: 2008-03-31
Abstract
Abstract A rounding circuit (10) for converting and rounding an M bit output from an adder array (12) into a N bit binary magnitude representation includes an incrementer (18) which increments the output of the adder array (12) prior to conversion. A borrow calculator (16) generates a select signal to a multiplexer indicating whether covnersion of the M bit number requires a borrow from the upper N bits. The select signal is used to choose between the incremented or non-incremented output. A converter/decrementer (22) converts the selected output of the multiplexer (20) into a binary magnitude number and also computes the magnitude representation decremented by one. A rounding circuitry (24) computes the rounding direction based on a control signal from control circuitry (26). The rounder circuit (10) calculates rounding information for two cases: (a) assuming that no normalization of the converted value is necessary and (b) assuming that normalization of the converted value is necessary. A selector/shifter (28) chooses between the decremented and non-decremented values based on the rounding information.
Inventors
- 👤 Henry M. Darley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:39
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/487; G06F7/4876; G06F7/499; G06F7/49936; G06F7/49942; G06F7/49947
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
84 words
A rounding circuit for converting and rounding an M bit output from an adder array into an N bit binary magnitude representation comprising: conversion circuitry to convert predetermined portions of said M bit output into a binary magnitude representation; rounding circuitry to calculate rounding information for said M bit output simultaneously with the converting of the portions of the M bit output; and output circuitry for forming the N bit magnitude representation, based on the outputs of said conversion circuitry and said rounding circuitry.
Claim 2
Dependent Claim
84 words
A rounding circuit for converting and rounding an M bit output from an adder array into an N bit binary magnitude representation comprising: conversion circuitry to convert predetermined portions of said M bit output into a binary magnitude representation; rounding circuitry to calculate rounding information for said M bit output simultaneously with the converting of the portions of the M bit output; and output circuitry for forming the N bit magnitude representation, based on the outputs of said conversion circuitry and said rounding circuitry.
Claim 3
Dependent Claim
45 words
The rounding circuit of claim 1 wherein said rounding circuitry comprises: circuitry to calculate said rounding information assuming no normalization of the converted M bit output is necessary; and circuitry to calculate said rounding information assuming normalization of the converted M bit output is necessary.
Claim 4
Dependent Claim
29 words
The rounding circuit of claim 2 wherein said circuitry to calculate rounding assuming normalization includes circuitry to calculate a least significant bit of the N bit binary magnitude representation.
Claim 5
Dependent Claim
93 words
The rounding circuit of claim 3 wherein said conversion circuitry generates a first value in which the most significant N bits of the adder array output are converted to magnitude representation assuming the rounding of the M bit magnitude representation does not result in a carry into the most significant N bits, and a second value in which the most significant N bits of the adder array output are converted to magnitude representation assuming the rounding of the M bit magnitude representation does result in a carry into the most significant N bits.
Claim 6
Dependent Claim
23 words
The rounding circuit of claim 4 wherein said output circuitry includes circuitry to detect whether normalization of said converted magnitude representation is necessary.
Claim 7
Dependent Claim
20 words
The rounding circuit of claim 5 wherein said output circuitry further includes shifting circuitry to normalize said converted magnitude representation.
Claim 8
Dependent Claim
29 words
The rounding circuit of claim 4 and further comprising incrementing circuitry for incrementing the output of the adder array prior to conversion to avoid carry chains due to rounding.
Claim 9
Dependent Claim
174 words
A rounding circuit for converting an M bit output of an adder array into a binary magnitude representation and rounding the output into a N bit number, comprising: incrementing circuitry for incrementing the most significant N bits of the adder array output by one; borrow calculation circuitry for determining whether conversion of the M bit output results in a borrow from the most significant N bits; multiplexer circuitry for selecting an output between the most significant N bits of the adder array output and the incremented output based on the determination by said borrow calculation circuitry; converter/decrementer circuitry for converting said selected output from the multiplexer circuitry into a binary magnitude number for calculating a decremented binary magnitude number; rounding circuitry receiving an output of the borrow calculation circuitry for calculating the direction of a round of the adder array output; and selector circuitry receiving outputs of said converter/decrementer circuitry and said rounding circuitry for selecting between said decremented and non-decremented numbers calculated by said converter/decrementer based on the output of the rounding circuitry.
Claim 10
Dependent Claim
174 words
A rounding circuit for converting an M bit output of an adder array into a binary magnitude representation and rounding the output into a N bit number, comprising: incrementing circuitry for incrementing the most significant N bits of the adder array output by one; borrow calculation circuitry for determining whether conversion of the M bit output results in a borrow from the most significant N bits; multiplexer circuitry for selecting an output between the most significant N bits of the adder array output and the incremented output based on the determination by said borrow calculation circuitry; converter/decrementer circuitry for converting said selected output from the multiplexer circuitry into a binary magnitude number for calculating a decremented binary magnitude number; rounding circuitry receiving an output of the borrow calculation circuitry for calculating the direction of a round of the adder array output; and selector circuitry receiving outputs of said converter/decrementer circuitry and said rounding circuitry for selecting between said decremented and non-decremented numbers calculated by said converter/decrementer based on the output of the rounding circuitry.
Claim 11
Dependent Claim
41 words
The rounding circuit of claim 8 and further comprising rounding converter circuitry for converting the lower M-N bits of the adder array output into a binary magnitude number, said rounding circuitry calculating the rounding direction based on said converted M-N bits.
Claim 12
Dependent Claim
96 words
The rounding circuit of claim 8 wherein the adder is a signed digit adder and further comprising: circuitry to calculate a sticky bit equal to the most significant non-zero bit of the output of the adder array from bit position M-(N-3) to bit position zero, the sticky bit equal to zero if all of the bits equal zero; and circuitry for converting bits of the adder array output corresponding to bit positions M-(N-1), and M-(N-2), and said sticky bit, into a binary magnitude number, said rounding circuitry calculating the rounding direction based on said converted bits.
Claim 13
Dependent Claim
15 words
The rounding circuit of claim 8 wherein said converter/decrementer circuitry comprises a carry select subtracter.
Claim 14
Dependent Claim
20 words
The rounding circuit of claim 8 and further comprising circuitry for selectively shifting said number selected by said selector circuitry.
Claim 15
Dependent Claim
31 words
The rounding circuit of claim 12 and further comprising shift control means for determining whether a shift is necessary based on the most significant bits of said decremented and non-decremented numbers.
Claim 16
Dependent Claim
43 words
The rounding circuit of claim 13 wherein said rounding circuitry comprises circuitry to calculate a first rounding direction based on the M-N bits of the adder array output and a second rounding direction based on the M-(N-1) bits of the adder array output.
Claim 17
Dependent Claim
34 words
The rounding circuit of claim 14 wherein said rounding circuitry further comprises circuitry to calculate a least significant bit for the N bit output for the case where said shifting circuitry performs a shift.
Claim 18
Dependent Claim
44 words
The rounding circuit of claim 15 wherein said rounding circuitry further includes circuitry to output a first select signal based on said calculated first rounding direction and a second select signal based on said calculated second rounding direction and said calculated least significant bit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-08 | 1996-06-08 | 1996-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-08 | 2000-06-08 | 2000-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-08 | 2004-06-08 | 2004-12-08 | $7700.00 | Window Closed / Lapsed |