US5168336A
Expired / Lapsed
US
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Dynamic random access memory device with trench type memory cell
Assignee: NEC Electronics Corp
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Filing: 1991-06-27
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Granted: 1992-12-01
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Expires: 2011-06-27
Abstract
Abstract A dynamic random access memory cell comprises a switching transistor and a storage capacitor formed in a relatively deep trench and having a capacitor electrode projecting over the major surface of the semiconductor substrate, wherein the switching transistor comprises a source/drain region formed along a wall portion defining the relatively deep trench, another source/drain region formed in the major surface portion, a channel region extending partially along a wall portion defining a relatively shallow trench and partially beneath the major surface so that a channel length is prolonged, thereby decreasing an occupation area without any punch-through phenomenon.
Inventors
- 👤 Hiroaki Mikoshiba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:27
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/34; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10B12/37; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
160 words
A dynamic random access memory device fabricated on a semiconductor substrate having a major surface, comprising: a memory cell array having a plurality of memory cells, each of said memory cells comprising a) a storage capacitor formed in a relatively deep trench exposed to said major surface, and having an electrode projecting from said major surface; and b) a switching transistor having b-1) a first impurity region extending along a wall portion defining said relatively deep trench, b-2) a second impurity region formed in a major surface portion of said semiconductor substrate beneath said major surface, b-3) a channel region electrically interconnecting said first and second impurity regions and extending partially along another wall portion defining a relatively shallow trench exposed to said major surface and partially beneath said major surface, b-4) a gate insulating film extending partially on said another wall portion and partially on said major surface, and b-5) a gate electrode formed on said gate insulating film.
Claim 2
Dependent Claim
160 words
A dynamic random access memory device fabricated on a semiconductor substrate having a major surface, comprising: a memory cell array having a plurality of memory cells, each of said memory cells comprising a) a storage capacitor formed in a relatively deep trench exposed to said major surface, and having an electrode projecting from said major surface; and b) a switching transistor having b-1) a first impurity region extending along a wall portion defining said relatively deep trench, b-2) a second impurity region formed in a major surface portion of said semiconductor substrate beneath said major surface, b-3) a channel region electrically interconnecting said first and second impurity regions and extending partially along another wall portion defining a relatively shallow trench exposed to said major surface and partially beneath said major surface, b-4) a gate insulating film extending partially on said another wall portion and partially on said major surface, and b-5) a gate electrode formed on said gate insulating film.
Claim 3
Dependent Claim
25 words
A dynamic random access memory device as set forth in claim 1, in which said relatively shallow trench is contiguous to said relatively deep trench.
Claim 4
Dependent Claim
34 words
A dynamic random access memory device as set forth in claim 2, in which said channel region has a predetermined length long enough to prevent said switching transistor from exhibiting a punch-through effect phenomenon.
Claim 5
Dependent Claim
68 words
A dynamic random access memory device as set forth in claim 3, in which said another wall portion has a bottom surface and a vertical surface of about 0.5 micron in length, and in which the total length of said bottom surface between said first impurity region and said vertical surface and said major surface between said second impurity region and said vertical surface is about 0.5 micron.
Claim 6
Dependent Claim
108 words
A dynamic random access memory device as set forth in claim 4, in which said gate electrode is covered with an inter-level insulating film having a through hole substantially aligned with said relatively deep trench, and in which said storage capacitor comprises a-1) said electrode projecting from said relatively deep trench as well as said through hole and extending on said inter-level insulating film so as to be partially overlapped with said gate electrode, said electrode defining a secondary trench, a-2) a dielectric film structure covering said electrode and defining a tertiary trench, and a-3) a counter electrode filling said tertiary trench and extending on said dielectric film.
Claim 7
Dependent Claim
26 words
A dynamic random access memory device as set forth in claim 1, in which said relatively shallow trench is spaced apart from said relatively deep trench.
Claim 8
Dependent Claim
42 words
A dynamic random access memory device, as set forth in claim 6, in which said relatively shallow trench has two vertical surfaces and a bottom surface, and in which said channel region extends along said two vertical surfaces and said bottom surface.
Claim 9
Dependent Claim
108 words
A dynamic random access memory device as set forth in claim 7, in which said gate electrode is covered with an inter-level insulating film having a through hole substantially aligned with said relatively deep trench, and in which said storage capacitor comprises a-1) said electrode projecting from said relatively deep trench as well as said through hole and extending on said inter-level insulating film so as to be partially overlapped with said gate electrode, said electrode defining a secondary trench, a-2) a dielectric film structure covering said electrode and defining a tertiary trench, and a-3) a counter electrode filling said tertiary trench and extending on said dielectric film.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-01 | 1996-06-01 | 1996-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-01 | 2000-06-01 | 2000-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-01 | 2004-06-01 | 2004-12-01 | $7700.00 | Window Closed / Lapsed |