System for controlling task operation of slave processor by switching access to shared memory banks by master processor

Claim 1

A method for controlling the operation of a slave processor by a master processor using multiple banks of memory, comprising in combination the steps of: making instruction code task information in all banks such that they begin at a consistent starting offset address within each bank and finish by returning to the same starting offset address; allowing the slave processor to execute instruction code information stored in a first bank to perform a task; monitoring the memory offset address where the slave processor is operating in the first bank; delaying a pending switch to a second bank that the master processor has requested until just before the slave processor reads the first instruction of the next task at the memory offset address, whereby the slave processor can complete the current task and smoothly switch to the next task with substantially no software overhead required of either the master processor or the slave processor; and switching by the master processor of the functional position of the banks whereby the slave processor executes instruction code information stored in another bank to perform another task.

Claim 2

A method for controlling the operation of a slave processor by a master processor using multiple banks of memory, comprising in combination the steps of: making instruction code task information in all banks such that they begin at a consistent starting offset address within each bank and finish by returning to the same starting offset address; allowing the slave processor to execute instruction code information stored in a first bank to perform a task; monitoring the memory offset address where the slave processor is operating in the first bank; delaying a pending switch to a second bank that the master processor has requested until just before the slave processor reads the first instruction of the next task at the memory offset address, whereby the slave processor can complete the current task and smoothly switch to the next task with substantially no software overhead required of either the master processor or the slave processor; and switching by the master processor of the functional position of the banks whereby the slave processor executes instruction code information stored in another bank to perform another task.