US5166937A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arrangement for testing digital circuit devices having tri-state outputs
Assignee: AG Communication Systems Corp
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Filing: 1990-12-26
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Granted: 1992-11-24
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Expires: 2010-12-26
Abstract
Abstract An arrangement is disclosed that is added to digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group.
Inventors
- 👤 John F. Blecha, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/31855
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
681 words
An arrangement for testing the inputs and outputs of a digital circuit device, said digital circuit device including a plurality of inputs and outputs arranged in sequential groups, and a test mode control input for activating said arrangement, said arrangement comprising: a first test signal input circuit connected to the first input of said sequential group, said first test signal input circuit arranged to receive a test signal applied to said first input and to pass said test signal to said first sequential group input, and to an included test out lead; a second test signal input circuit including gate means having a first input lead connected to a test out lead, and a second input lead connected to the next input of said sequential group, said gate means arranged to exclusively combine the test signal received on said second input with the test signal received on said first input and to generate and output a test out signal from an included test out lead; a first test signal output circuit including a first input connected to an output of said sequential group that is not the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said test out signal, an enable test control lead for selecting between said first and second inputs, a standard output lead for passing the signal selected, and a test out lead connected to said second input inverted signal for passing said inverted test signal to the next test circuit; a second test signal output circuit including a first input connected to an output of said sequential group that is the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said input test out signal, an enable test control lead for selecting between said first and said second inputs, and a standard output lead for passing the signal selected for input; a first test signal tri-state output circuit including a first input connected to an output of said sequential group that is not the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said test out signal, an enable test control lead for selecting between said first and second inputs, gate means having an output and a first input connected to said enable test control lead and a second input connected to a driver control input from said digital circuit device, a tri-state gate having an output, an input connected to an output lead of said first test signal tri-state output circuit and an enabling input connected to said gate means output, said gate means enabling said tri-state gate to pass said input signal selected, and a test out lead connected to said second input inverted signal for passing said inverted test signal to the next test circuit; and a second test signal tri-state output circuit including a first input connected to an output of said sequential group that is the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said input test out signal, an enable test control lead for selecting between said first and said second inputs, gate means having an output and a first input connected to said enable test control lead and a second input connected to a driver control input from said digital circuit device, a tri-state gate having an output, an input connected to an output lead of said first test signal tri-state output circuit, and an enabling input connected to said gate means output, said gate means enabling said tri-state gate to pass the input signal selected, whereby said test signal input into said first test signal input circuit is output at said second test signal tri-state gate output.
Claim 2
Dependent Claim
681 words
An arrangement for testing the inputs and outputs of a digital circuit device, said digital circuit device including a plurality of inputs and outputs arranged in sequential groups, and a test mode control input for activating said arrangement, said arrangement comprising: a first test signal input circuit connected to the first input of said sequential group, said first test signal input circuit arranged to receive a test signal applied to said first input and to pass said test signal to said first sequential group input, and to an included test out lead; a second test signal input circuit including gate means having a first input lead connected to a test out lead, and a second input lead connected to the next input of said sequential group, said gate means arranged to exclusively combine the test signal received on said second input with the test signal received on said first input and to generate and output a test out signal from an included test out lead; a first test signal output circuit including a first input connected to an output of said sequential group that is not the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said test out signal, an enable test control lead for selecting between said first and second inputs, a standard output lead for passing the signal selected, and a test out lead connected to said second input inverted signal for passing said inverted test signal to the next test circuit; a second test signal output circuit including a first input connected to an output of said sequential group that is the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said input test out signal, an enable test control lead for selecting between said first and said second inputs, and a standard output lead for passing the signal selected for input; a first test signal tri-state output circuit including a first input connected to an output of said sequential group that is not the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said test out signal, an enable test control lead for selecting between said first and second inputs, gate means having an output and a first input connected to said enable test control lead and a second input connected to a driver control input from said digital circuit device, a tri-state gate having an output, an input connected to an output lead of said first test signal tri-state output circuit and an enabling input connected to said gate means output, said gate means enabling said tri-state gate to pass said input signal selected, and a test out lead connected to said second input inverted signal for passing said inverted test signal to the next test circuit; and a second test signal tri-state output circuit including a first input connected to an output of said sequential group that is the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said input test out signal, an enable test control lead for selecting between said first and said second inputs, gate means having an output and a first input connected to said enable test control lead and a second input connected to a driver control input from said digital circuit device, a tri-state gate having an output, an input connected to an output lead of said first test signal tri-state output circuit, and an enabling input connected to said gate means output, said gate means enabling said tri-state gate to pass the input signal selected, whereby said test signal input into said first test signal input circuit is output at said second test signal tri-state gate output.
References Cited (Backward Citations)
US4583223A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-24 | 1996-05-25 | 1996-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-24 | 2000-05-25 | 2000-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-24 | 2004-05-25 | 2004-11-24 | $7700.00 | Window Closed / Lapsed |