US5166808A
Expired / Lapsed
US
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Digital binarization circuit for conversion of image data
Assignee: Mitsubishi Electric Corp
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Filing: 1989-11-16
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Granted: 1992-11-24
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Expires: 2009-11-16
Abstract
Abstract A digital binarization circuit for image data includes a background level detecting circuit which uses a video signal as a reference input for determining the background level of an image represented by the video signal, and outputs the background level as a first address signal. A character level detecting circuit compares the video signal with a character level in a load decision comparator and loads the video signal as a character level when the signal is less than the reference level, and outputs the character level as a second address signal. A memory circuit ouputs a threshold value stored at an address designated by the first and second address signals to a comparator. The optimum threshold value is outputted among prescribed threshold values stored in the memory circuit. The comparator compares the digitized video signal with the optimum threshold value and outputs a binary signal corresponding to the comparison result. Even for original documents with a dark background, noise is not liable to occur in the transmitted video signal, and a light character can appear clearly on the transmitted video signal.
Inventors
- 👤 Toshiyuki Kawata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:20
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/403; G; G06; G06V; G06V30/00; G06V30/10; G06V30/16; G06V30/162
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
155 words
A digital binarization circuit, wherein an analog image signal representing an image is converted into a digital image signal of n-bits per pixel, n being an integer, comprising: background level detecting means for generating a background level signal corresponding to the background level of said image; character level detecting means for detecting the level of a character in said image and generating a character level signal corresponding thereto; memory means storing a set of predetermined threshold values and responsive to said background and character level signals as first and second address signals for outputting a particular threshold value stored at an address corresponding to said address signals; and comparator means for comparing said digital image signal with said outputted threshold value and outputting a high level signal when said digital image signal is greater than said outputted threshold value, and a low level signal when said digital image signal is less than said threshold value.
Claim 2
Dependent Claim
155 words
A digital binarization circuit, wherein an analog image signal representing an image is converted into a digital image signal of n-bits per pixel, n being an integer, comprising: background level detecting means for generating a background level signal corresponding to the background level of said image; character level detecting means for detecting the level of a character in said image and generating a character level signal corresponding thereto; memory means storing a set of predetermined threshold values and responsive to said background and character level signals as first and second address signals for outputting a particular threshold value stored at an address corresponding to said address signals; and comparator means for comparing said digital image signal with said outputted threshold value and outputting a high level signal when said digital image signal is greater than said outputted threshold value, and a low level signal when said digital image signal is less than said threshold value.
Claim 3
Dependent Claim
132 words
A digital binarization circuit according to claim 1, wherein said background level detecting means comprises: an up/down counter for outputting said background level signal; an up/down selecting comparator having one input coupled to receive said background level signal, another input coupled to receive said digital image signal, and a selector output coupled to an up/down input of said counter for selecting a count up state of said counter when said digital image signal is greater than said background level signal and a count down state otherwise; and a selector coupled to the output of said selecting comparator for selecting a background up clock as a clock input to said counter in said count up state and a background down clock as a clock input to said counter in said count down state.
Claim 4
Dependent Claim
111 words
A digital binarization circuit according to claim 1, wherein said character level detecting means comprises: a preset counter for outputting said character level signal; and a load decision comparator having one input coupled to receive said character level signal, another input coupled to receive said digital image signal, and an output coupled to a load input of said preset counter for instructing said counter to load said digital image signal as said character level signal when said digital image signal is less than the character level signal inputted to said comparator, and instructing said counter to count up when said digital image signal is greater than said inputted character level signal.
Claim 5
Dependent Claim
143 words
A digital binarization circuit, wherein an analog image signal representing an image is converted into a digital image signal of n-bits per pixel, n being an integer, comprising: background level detecting means for generating a background level signal corresponding to the background level of said image; density changing means for outputting a density changing signal for varying a threshold value to which said digital image signal is compared; an adder which adds said background level signal and said density changing signal to form an n-bit signal corresponding to said threshold value at an output thereof; and comparator means for comparing said digital image signal with said outputted threshold value and outputting a high level signal when said digital image signal is greater than said outputted threshold value, and a low level signal when said digital image signal is less than said threshold value.
Claim 6
Dependent Claim
143 words
A digital binarization circuit, wherein an analog image signal representing an image is converted into a digital image signal of n-bits per pixel, n being an integer, comprising: background level detecting means for generating a background level signal corresponding to the background level of said image; density changing means for outputting a density changing signal for varying a threshold value to which said digital image signal is compared; an adder which adds said background level signal and said density changing signal to form an n-bit signal corresponding to said threshold value at an output thereof; and comparator means for comparing said digital image signal with said outputted threshold value and outputting a high level signal when said digital image signal is greater than said outputted threshold value, and a low level signal when said digital image signal is less than said threshold value.
Claim 7
Dependent Claim
132 words
A digital binarization circuit according to claim 4, wherein said background level detecting means comprises: an up/down counter for outputting said background level signal; an up/down selecting comparator having one input coupled to receive said background level signal, another input coupled to receive said digital image signal, and a selector output coupled to an up/down input of said counter for selecting a count up state of said counter when said digital image signal is greater than said background level signal and a count down state otherwise; and a selector coupled to the output of said selecting comparator for selecting a background up clock as a clock input to said counter in said count up state and a background down clock as a clock input to said counter in said count down state.
Claim 8
Dependent Claim
273 words
A digital binarization circuit, wherein an analog image signal representing an image is converted into a digital image signal of n-bits per pixel, n being an integer, comprising: background level detecting means for generating a background level signal corresponding to the background level of said image, including an up/down counter for outputting said background level signal, an up/down selecting comparator having one input coupled to receive said background level signal, another input coupled to receive said digital image signal, and a selector output coupled to an up/down input of said counter for selecting a count up state of said counter when said digital image signal is greater than said background level signal and a count down state otherwise, and a selector coupled to the output of said selecting comparator for selecting a background up clock as a clock input to said counter in said count up state and a background down clock as a clock input to said counter in said count down state; character level detecting means for detecting the level of a character in said image and generating a character level signal corresponding thereto; memory means storing a set of predetermined threshold values and responsive to said background and character level signals as first and second address signals for outputting a particular threshold value stored at an address corresponding to said address signals; and comparator means for comparing said digital image signal with said outputted threshold value and outputting a high level signal when said digital image signal is greater than said outputted threshold value, and a low level signal when said digital image signal is less than said threshold value.
Claim 9
Dependent Claim
273 words
A digital binarization circuit, wherein an analog image signal representing an image is converted into a digital image signal of n-bits per pixel, n being an integer, comprising: background level detecting means for generating a background level signal corresponding to the background level of said image, including an up/down counter for outputting said background level signal, an up/down selecting comparator having one input coupled to receive said background level signal, another input coupled to receive said digital image signal, and a selector output coupled to an up/down input of said counter for selecting a count up state of said counter when said digital image signal is greater than said background level signal and a count down state otherwise, and a selector coupled to the output of said selecting comparator for selecting a background up clock as a clock input to said counter in said count up state and a background down clock as a clock input to said counter in said count down state; character level detecting means for detecting the level of a character in said image and generating a character level signal corresponding thereto; memory means storing a set of predetermined threshold values and responsive to said background and character level signals as first and second address signals for outputting a particular threshold value stored at an address corresponding to said address signals; and comparator means for comparing said digital image signal with said outputted threshold value and outputting a high level signal when said digital image signal is greater than said outputted threshold value, and a low level signal when said digital image signal is less than said threshold value.
Claim 10
Dependent Claim
111 words
A digital binarization circuit according to claim 6, wherein said character level detecting means comprises: a preset counter for outputting said character level signal; and a load decision comparator having one input coupled to receive said character level signal, another input coupled to receive said digital image signal, and an output coupled to a load input of said preset counter for instructing said counter to load said digital image signal as said character level signal when said digital image signal is less than the character level signal inputted to said comparator, and instructing said counter to count up when said digital image signal is greater than said inputted character level signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-24 | 1996-05-25 | 1996-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-24 | 2000-05-25 | 2000-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-24 | 2004-05-25 | 2004-11-24 | $7700.00 | Window Closed / Lapsed |